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[79.100.18.255]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b6d511f8634sm518519566b.29.2025.10.24.05.34.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Oct 2025 05:34:42 -0700 (PDT) Message-ID: <9594fa0e-22f6-4412-a967-6d5c1374da48@gmail.com> Date: Fri, 24 Oct 2025 15:34:41 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/5] clk: samsung: introduce exynos8890 clock driver Content-Language: en-US To: Peter Griffin , Krzysztof Kozlowski Cc: Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20251017161334.1295955-1-ivo.ivanov.ivanov1@gmail.com> <20251017161334.1295955-6-ivo.ivanov.ivanov1@gmail.com> <20251022-savvy-sly-auk-a60073@kuoka> From: Ivaylo Ivanov In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/24/25 15:07, Peter Griffin wrote: > Hi Ivaylo & Krzysztof, > > On Wed, 22 Oct 2025 at 08:56, Krzysztof Kozlowski wrote: >> On Fri, Oct 17, 2025 at 07:13:33PM +0300, Ivaylo Ivanov wrote: >>> Introduce a clocks management driver for exynos8890, providing clocks >>> for the peripherals of that SoC. >>> >>> As exynos8890 is the first exynos SoC to feature Hardware Auto Clock >>> Gating (HWACG), it differs from newer SoCs. Q-channel and Q-state bits >>> are separate registers, unlike the CLK_CON_GAT_* ones that feature HWACG >>> bits in the same register that controls manual gating. Hence, don't use >>> the clk-exynos-arm64 helper, but implement logic that enforces manual >>> gating. > For sure it isn't the only upstream SoC with HWACG, gs101 and e850 and > probably lots of Exynos SoCs have it. Whether it is the "first" in > terms of release date of the SoC I don't know Huh? Samsung hasn't released a lot of exynos chips and you're free to check kernel sources if curious. Exynos 7420 didn't have HWACG, 8890 and 8895 have it. Exynos 7870 (roughly same gen as 8890, but budget lineup) doesn't have it. > , unless there is some comment in > downstream code to that effect). Your CMU registers do look like a > different layout though. Exactly. First implementation/gen of HWACG == lots of room to improve. Which they did, and this is what I implied here. I can word it differently though, to be more clear. > Just fyi gs101 also has Q-Channel registers that contain HWACG Enable > bits. The reset state of all these bits on gs101 (both for QCH_CON_XXX > registers, QCH_EN bit and HWACG bit in CLK_CON_GAT_* regs is off). In > my case I suspect the bootloader doesn't initialize any of them > because of the CMUs "global enable override" bits in the CMU_OPTION > register (which is initialized by the bootloader). Well, to be fair, without any documentations or bootloader sources there's so much so I can do. The vendor kernel also force disables the qchannel registers, hence the assumption. >> Please CC @Peter Griffin in future versions. >> >> How much of this can be shared between this and GS101? >> https://lore.kernel.org/all/20251013-automatic-clocks-v1-0-72851ee00300@linaro.org/ >> > It seems from the commit description Ivaylo is still wanting to put > all the gates into manual mode, so is only initializing these > registers to ensure HWACG is disabled. Yeah. Not all CMU blocks seem to implement HWACG, so in my opinion it's best to just keep all in manual gating mode. > Happy to help review it though. Would love you to! Thanks! Best regards, Ivaylo