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[93.144.65.244]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490b63d8205sm33175305e9.11.2026.06.03.01.25.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jun 2026 01:25:08 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Subject: [PATCH v3 2/5] arm64: dts: imx93-var-som-symphony: enable UART7 Date: Wed, 3 Jun 2026 10:25:01 +0200 Message-ID: <95c0dbfea0536bc38cdc71d7451f99a3fa4aa08f.1780474803.git.stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Stefano Radaelli Enable UART7 on the Symphony carrier board and add its pinctrl configuration. Signed-off-by: Stefano Radaelli --- v2->v3: - v1->v2: - .../boot/dts/freescale/imx93-var-som-symphony.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts index c736127c7115..77377127c18c 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx93-var-som-symphony.dts @@ -35,6 +35,7 @@ aliases { serial3 = &lpuart4; serial4 = &lpuart5; serial5 = &lpuart6; + serial6 = &lpuart7; }; @@ -305,6 +306,12 @@ &lpuart6 { status = "okay"; }; +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -441,6 +448,13 @@ MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e >; }; + pinctrl_uart7: uart7grp { + fsl,pins = < + MX93_PAD_GPIO_IO09__LPUART7_RX 0x31e + MX93_PAD_GPIO_IO08__LPUART7_TX 0x31e + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e -- 2.47.3