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Tue, 17 Mar 2026 00:21:50 -0700 (PDT) X-Received: by 2002:a17:90b:3d4b:b0:359:c479:fc68 with SMTP id 98e67ed59e1d1-35a220aaff9mr9161903a91.5.1773732110083; Tue, 17 Mar 2026 00:21:50 -0700 (PDT) Received: from [10.218.41.33] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35badbcb8b9sm2417780a91.13.2026.03.17.00.21.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 17 Mar 2026 00:21:49 -0700 (PDT) Message-ID: <95d2de63-5571-4fce-aa32-6e8969bb9149@oss.qualcomm.com> Date: Tue, 17 Mar 2026 12:51:40 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 00/16] Support Armv8 RAS Extensions for Kernel-first error handling To: Ruidong Tian , catalin.marinas@arm.com, will@kernel.org, lpieralisi@kernel.org, guohanjun@huawei.com, sudeep.holla@arm.com, rafael@kernel.org, robin.murphy@arm.com, mark.rutland@arm.com, tony.luck@intel.com, bp@alien8.de, tglx@linutronix.de, peterz@infradead.org Cc: lenb@kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-edac@vger.kernel.org, mchehab@kernel.org, xueshuai@linux.alibaba.com, zhuo.song@linux.alibaba.com, oliver.yang@linux.alibaba.com References: <20260122094656.73399-1-tianruidong@linux.alibaba.com> Content-Language: en-US From: Umang Chheda In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: cQZHAqCqR0kHPwH4vnSD16cnaUgaKGLc X-Authority-Analysis: v=2.4 cv=aue/yCZV c=1 sm=1 tr=0 ts=69b9010f cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=VwQbUJbxAAAA:8 a=7CQSdrXTAAAA:8 a=IrbkRpuHRcUsFRyD9lEA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE3MDA2MyBTYWx0ZWRfX7SWUYB+NmHu7 egwFUUk5SJCbcubKQX5XCFKxA315Tg6Hrn3++oSv32P/tzXK/pIgdmSrO0BxppWvbUZ8mdUV+4Z hwl3D8Z6iHG0TEuuiW3FmSyrmiPHW9HRVgmKtSSyr+8cL4jvDaXYm686NI+Dt9IncWFo0S8ni8i MwuwFH21dcMP1yN6J3Eg9yb7w4Fh7RtQKNwRz4GFSAyuL613cmIlzs7D6dWcdl9FuJBu3C52M7z PfsNw5dwteYM3RzANLsw3e78SikJpu8mUCWuETUmNSOwZodo3DrO/NncM3F1KxvfZ+BONYA8hnp we9RKduiIisJdv/uASylGo4qrMnX6KPF/aGapOoFw0iRvndHq0ZFvr6TEvI/cByrR3VfJAQHAQ+ DjLoEaEF/rVAlXeceJXlnKmTabLls4iDreZr0dOYzpv8i1IjLcPF4dftRTBdR8BR4JU3uMqGxBl y6JOPpZGJOcfBY6qhLg== X-Proofpoint-GUID: cQZHAqCqR0kHPwH4vnSD16cnaUgaKGLc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-17_01,2026-03-16_06,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603170063 On 3/11/2026 8:55 AM, Ruidong Tian wrote: > > > 在 2026/3/9 21:28, Umang Chheda 写道: >> Hello Ruidong Tain, >> >> On 1/22/2026 3:16 PM, Ruidong Tian wrote: >>> Motivation: Reliability in Modern Data Centers >>> ================================================= >>> In modern data centers, proactive maintenance is essential for achieving high >>> service availability. The practice of using Corrected Errors (CE) to predict >>> impending Uncorrected Errors (UE) is already widely deployed at scale across >>> the industry, like Alibaba[2], Tencent[4], Intel[1], AMD[2]. By analyzing CE >>> telemetry, operators can identify failing hardware and perform migrations >>> before catastrophic failures occur. >>> >>> Problem: Inefficient CE Collection on ARM >>> ========================================== >>> Currently, ARM-based systems primarily rely on "Firmware-First" error >>> handling (e.g., via GHES). This path is inherently heavy-weight. To avoid >>> significant performance overhead, firmware is often configured with high >>> thresholds—reporting to the OS only after thousands of CEs have occurred. >>> If the threshold is set lower, the high frequency of errors leads to >>> excessive and costly context switching between the OS and firmware. >>> Consequently, ARM platforms currently lack an efficient mechanism to collect >>> the granular CE data required for high-fidelity error prediction. >>> >>> Solution: Kernel-First Handling via AEST >>> =========================================== >>> Other architectures have long utilized "Kernel-First" approaches for >>> efficient CE collection: Intel provides CMCI (Corrected Machine Check >>> Interrupt), and AMD has recently introduced similar CE interrupt support[5]. >>> >>> On the ARM architecture, hardware already provides the necessary RAS >>> Extensions[6], and the ACPI AEST specification[0] defines a standardized way for >>> the OS to discover these error source registers. This series implements >>> AEST support, enabling the kernel to: >>> >>>   - Discover error sources directly via ACPI tables. >>>   - Handle CE notifications via direct interrupts. >>>   - Bypass firmware overhead to collect every CE or use low-latency thresholds. >>> >>> This implementation provides the missing link for efficient RAS telemetry >>> on ARM, bringing it to parity with other enterprise architectures. >> >> Thanks for posting this series enabling kernel-first handling for the Armv8 RAS extensions. >> >> We noticed the current implementation targets ACPI-based server platforms. For embedded/SoC systems, Device Tree is often the primary firmware description. >> Do you have any plans to add DT-based support for the same flow? If not, do you see any blockers to extending this series to support DT >> (e.g., DT bindings + discovery/registration path analogous to the ACPI plumbing) ? >> If DT support is in-scope, We would be happy to align on the expected approach and help with review/development/testing for DT-based platforms. > > Hi Umang, > > Thanks for the reply. > > Adding Device Tree support should be easy. We just need a patch similar to "ACPI/AEST: Parse the AEST table" to fill the DT table into struct acpi_aest_node (might need renaming) and struct aest_hnode. The driver part requires minimal changes.  > > However, I'm not very familiar with DT and lack DT engineering support, so I would need some guidance on these DT-related questions: > > - Is there a specification that outlines the reporting     requirements for RAS extension information that is similar to AEST?  Currently there is no spec/bindings defined for DT based systems. Based on discussions on earlier posted patch [1]  - expectation from maintainers was to have DT bindings aligned to and equivalent to the AEST spec. Based on this expectation - we plan to propose DT bindings - which are  aligned to AEST spec. [1] Re: [PATCH 1/2] dt-bindings: edac: Add DT bindings for Kryo EDAC - James Morse > - How should the DT be designed? > Same as above - plan to align DT bindings equivalent to AEST spec. > - How can I develop QEMU and modify DT files for debugging, etc.?  We can share the steps for this for DT based system in this thread. > > I would be happy to adjust the patchset to meet the needs of both parties if you are prepared to invest the necessary effort（DT-related）. In reality, I believe that just a little modification is required.  Thanks, Yes - we are open to contribute in extending this patch series to support DT based systems as well. [...] Thanks, Umang > >> >>> >> >> >> >