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Wed, 04 Feb 2026 22:06:37 -0800 (PST) X-Received: by 2002:a17:903:3d0c:b0:2a7:683c:afb8 with SMTP id d9443c01a7336-2a933cf2c30mr55092505ad.16.1770271596900; Wed, 04 Feb 2026 22:06:36 -0800 (PST) Received: from [10.218.32.38] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a93394e635sm43375165ad.52.2026.02.04.22.06.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Feb 2026 22:06:36 -0800 (PST) Message-ID: <95d42fb7-2365-46a0-a995-c9cc51b17424@oss.qualcomm.com> Date: Thu, 5 Feb 2026 11:36:30 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/3] dt-bindings: interconnect: qcom,qcs615-rpmh: add clocks property to enable QoS To: Konrad Dybcio , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Raviteja Laggyshetty , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mike Tipton References: <20260202070534.1281652-1-odelu.kukatla@oss.qualcomm.com> <20260202070534.1281652-2-odelu.kukatla@oss.qualcomm.com> Content-Language: en-US From: Odelu Kukatla In-Reply-To: Content-Type: text/plain; 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For that node, >> driver must enable the corresponding clock(s) before accessing >> the registers. Add the 'clocks' property so the driver can obtain >> and enable the required clock(s). >> >> Only interconnects that have clock‑gated QoS register interface >> use this property; it is not applicable to all interconnect nodes. >> >> Signed-off-by: Odelu Kukatla >> --- >> .../interconnect/qcom,qcs615-rpmh.yaml | 44 +++++++++++++++++++ >> 1 file changed, 44 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml >> index e06404828824..096a9064cc01 100644 >> --- a/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml >> +++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs615-rpmh.yaml >> @@ -34,6 +34,10 @@ properties: >> reg: >> maxItems: 1 >> >> + clocks: >> + minItems: 3 >> + maxItems: 3 >> + >> required: >> - compatible >> >> @@ -53,6 +57,36 @@ allOf: >> required: >> - reg >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,qcs615-aggre1-noc >> + then: >> + properties: >> + clocks: >> + items: >> + - description: aggre UFS PHY AXI clock >> + - description: aggre USB2 SEC AXI clock >> + - description: aggre USB3 PRIM AXI clock > > Should we also include the IPA clock here? > Thanks for the review! For QCS615, the IPA clock is already enabled by the bootloader (xBL) and kept on during the boot‑up stage. Because of this, we do not need to explicitly enable the IPA clock in the interconnect driver when accessing the QoS registers. Thanks, Odelu > Konrad