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Tue, 01 Apr 2025 00:17:21 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFr4gOlMNdHJzyZphobs28BNbuI4vi69zmTSjUxMF19Ghg9xXQwTQ1pg7rC685uTI4i0vHJiA== X-Received: by 2002:a17:90b:134d:b0:2f8:4a3f:dd2d with SMTP id 98e67ed59e1d1-305320ae2eamr18234674a91.15.1743491840854; Tue, 01 Apr 2025 00:17:20 -0700 (PDT) Received: from [10.92.192.202] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2291f1ecb62sm81122505ad.230.2025.04.01.00.17.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 01 Apr 2025 00:17:20 -0700 (PDT) Message-ID: <95db82e9-8527-0520-07db-672e64b6e25b@oss.qualcomm.com> Date: Tue, 1 Apr 2025 12:47:15 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 2/2] PCI: Add support for PCIe wake interrupt Content-Language: en-US To: Lukas Wunner Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Bjorn Helgaas , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com References: <20250401-wake_irq_support-v1-0-d2e22f4a0efd@oss.qualcomm.com> <20250401-wake_irq_support-v1-2-d2e22f4a0efd@oss.qualcomm.com> From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: k9C-x7hYDaXC3jjL7V5CN2VlRIpnEmKG X-Authority-Analysis: v=2.4 cv=fdaty1QF c=1 sm=1 tr=0 ts=67eb9302 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=i3ooZJLN8YTFS9vXi5sA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: k9C-x7hYDaXC3jjL7V5CN2VlRIpnEmKG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-01_02,2025-03-27_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 malwarescore=0 suspectscore=0 spamscore=0 impostorscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=742 clxscore=1015 adultscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504010048 On 4/1/2025 12:31 PM, Lukas Wunner wrote: > On Tue, Apr 01, 2025 at 10:12:44AM +0530, Krishna Chaitanya Chundru wrote: >> PCIe wake interrupt is needed for bringing back PCIe device state >> from D3cold to D0. >> >> Implement new functions, of_pci_setup_wake_irq() and >> of_pci_teardown_wake_irq(), to manage wake interrupts for PCI devices >> using the Device Tree. >> >> From the port bus driver call these functions to enable wake support >> for bridges. > [...] >> --- a/drivers/pci/pcie/portdrv.c >> +++ b/drivers/pci/pcie/portdrv.c >> @@ -695,6 +695,10 @@ static int pcie_portdrv_probe(struct pci_dev *dev, >> if (type == PCI_EXP_TYPE_RC_EC) >> pcie_link_rcec(dev); >> >> + status = of_pci_setup_wake_irq(dev); >> + if (status) >> + return status; >> + >> status = pcie_port_device_register(dev); >> if (status) >> return status; >> @@ -728,6 +732,8 @@ static void pcie_portdrv_remove(struct pci_dev *dev) >> pm_runtime_dont_use_autosuspend(&dev->dev); >> } >> >> + of_pci_teardown_wake_irq(dev); >> + >> pcie_port_device_remove(dev); >> >> pci_disable_device(dev); > > Why doesn't the teardown order mirror the probe order, i.e. why is > of_pci_teardown_wake_irq() called *before* pcie_port_device_remove() > instead of after? > ack, in the next patch I will move teardown after pcie_port_device_remove() > (pcie_port_device_remove() is the opposite of pcie_port_device_register().) > > Also, why is it safe to bail out of probe on failure of > of_pci_setup_wake_irq() without unwinding whatever pcie_link_rcec() > has done? I think this needs either an explanation or reordering. > if there is a failure in port_device_register also we are not unwinding so I taught it is already taken care. Looks like it is not. In the next patch I will move of_pci_setup_wake_irq() above pcie_link_rcec() to avoid all this. - Krishna Chaitanya. > Thanks, > > Lukas