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Tue, 07 Jul 2026 03:29:15 -0700 (PDT) X-Received: by 2002:a17:902:d4cf:b0:2c9:b480:f5d0 with SMTP id d9443c01a7336-2ccbf053e65mr47340995ad.39.1783420154594; Tue, 07 Jul 2026 03:29:14 -0700 (PDT) Received: from [10.92.203.183] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ccc9d1e28fsm9213955ad.43.2026.07.07.03.29.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Jul 2026 03:29:14 -0700 (PDT) Message-ID: <95e256bd-191f-40df-96b4-6cff38473c5b@oss.qualcomm.com> Date: Tue, 7 Jul 2026 15:59:09 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: eliza: Add PCIe PHY and controller nodes To: Konrad Dybcio , Abel Vesa Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260610-eliza_dt-v1-1-7bb72b75fc5b@oss.qualcomm.com> <9448e854-d64f-4316-8fdd-4e1e3dcc9ce0@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <9448e854-d64f-4316-8fdd-4e1e3dcc9ce0@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: GwurxysJXSJ3yCmRdLtPof1pTz3zDeoa X-Proofpoint-ORIG-GUID: GwurxysJXSJ3yCmRdLtPof1pTz3zDeoa X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA3MDEwMSBTYWx0ZWRfXwuDUc3+gUacG cCteM0tKYfvyIX31BbxAyE7GD18L+zHw2/Nq45drLOsFxJ4tQ1g1Rmk47ANAmCavzw7WQtfAM1s bs6QydcHesvbDXsFf3iA3dSq7K84zJheC84hu07VRm5KD5BO4nW2Wx/ptMdNVeTMDO2Lcb3YULM zsSsjsJoQ9r9xHzopYXFPhbZyhoX9GzpZfmf+Sa0uMRyNSo295aMCQcclDdtMpaNe7Sy9vQaMAp K1QBoy1ECs2POwG5nbawHkDok+uKOCoZN2xgCIqmeqsk3//oKud4U6Tzjk2es0bS2C7k3NBmORQ hE/a0nC40gSpLcZcsoFYNwe6Ee+X5qg3Q2HpDKiM/LsaSN99f6WzK8dr4dB7pyHny5oo1ATpvyq r3FPHl2YYyHVujv71DKS67mawNwOjLvL0wQN5bXe/IRZwxmrH6JkqwoXSZpGwUt39fH/WyFVZXn H1rwOw6eciRGc19vO5Q== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA3MDEwMSBTYWx0ZWRfX0LRkABz5gCcE kLO+fPe89Oeu45uezb1N0l32DblrUUiyqkgkcDRLpem/UfCQXrAMg+KeOOaiRf5rQZf6rDLjjoM FLCOPIGwaUzrIopg2wXcFQm8lDTqKnA= X-Authority-Analysis: v=2.4 cv=atSCzyZV c=1 sm=1 tr=0 ts=6a4cd4fb cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=qQ0QJl8GeCU3ww7rcdMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-07_02,2026-07-06_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 clxscore=1015 priorityscore=1501 spamscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607070101 On 7/7/2026 3:55 PM, Konrad Dybcio wrote: > On 6/26/26 5:15 PM, Abel Vesa wrote: >> On 26-06-26 09:46:03, Krishna Chaitanya Chundru wrote: >>> >>> On 6/25/2026 3:42 PM, Abel Vesa wrote: >>>> On 26-06-10 17:40:09, Krishna Chaitanya Chundru wrote: >>>>> Eliza supports two PCIe instances: one 8GT/s x1 (PCIe0) and one 8GT/s x2 >>>>> (PCIe1). Add PCIe controller and PHY nodes for both instances, and update >>>>> the GCC clock references to use the newly added PHY nodes instead of >>>>> placeholder zeros. >>>>> >>>>> Signed-off-by: Krishna Chaitanya Chundru >>>>> --- > [...] > >>>> No pinctrl states? >>> As we are adding perst & wake gpio's in board specific file, it is better to >>> add the pincntrl also >>> there only. >> I'll let Bjorn and Konrad reply, but most of the sm8*50.dtsi have >> them. Though some of the newer platforms moved them in the board dts. > Some folks argue (I believe purely ideologically) that the pin states > should be defined in the board DTSI, but I don't think we have a single > example of non-default routing in the many many years of linux-arm-msm, > so I think the reasonable decision is to keep them in the SoC DTSI. ack. I will re-spin  - Krishna Chaitanya. > > Konrad