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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-kernel@vger.kernel.org, netdev@vger.kernel.org Subject: Re: [PATCH v2 16/24] net: phy: Add Sanechips ZX5201 PHY support Message-ID: <95e7fc97-2bd1-4b68-a9ef-246302ed9ec7@lunn.ch> References: <20261014072109.1759502-1-ghahramani.navid@gmail.com> <20261014072109.1759502-17-ghahramani.navid@gmail.com> <788c9b01-473e-4c45-b6f0-b2ba054da8e9@lunn.ch> <20261113003655.3665572-1-ghahramani.navid@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261113003655.3665572-1-ghahramani.navid@gmail.com> > > We need to understand this, because if it is an RGMII PHY, we need to > > address the RGMII delays, which that page says it can controller. > > That part I still have to find out. My driver has always told phylib > gmii and the WAN port runs at 1 Gbs, but I have not worked out yet > what the link between the SoC and the ZX5201 really is. https://www.sanechips.com.cn/en/Products/WiredEn/fixedNetworkTerminalEn/1558027080778723330.html This says it is RGMII. > SerDes was just the name I gave the registers at the second address, > and there is no public documentation for them. I will find out what > the interface is, and how the delays are set if it is RGMII, before > I send the networking patches again. So picking SERDES is probably causing some of this confusion. SERDES implies there is a PCS, and the PCS is doing signalling for SGMII or 1000BaseX. With RGMII, none of that exists. The registers might be controlling clocks, or regulators etc. https://www.sanechips.com.cn/en/ProductEn/WiredEn/ethernetConnectivityEn/index.html Also says RGMII. Andrew