From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from CH4PR04CU002.outbound.protection.outlook.com (mail-northcentralusazon11013062.outbound.protection.outlook.com [40.107.201.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74FAF358D1C for ; Fri, 16 Jan 2026 09:43:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.201.62 ARC-Seal:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768556617; cv=fail; b=BzeYhbkBZ6o06MdSUFj9z8rJ0J5sYtBEtJk68ON6WMluIq4p0AWZg0nQjFagAAvBcBPzFC3bVCHb5dbXzD+CyaFZrm0kxr3Oc+b+NHu7rdcmOyxF/TDqKrgO6yZK2BjsoFCq5z8QKRiGr/CmLGuVdePgZIFh4tJrU1BkJc4U6GA= ARC-Message-Signature:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768556617; c=relaxed/simple; bh=PxpCiaSzCxENVYFux+g28E1JoD0rd7F98n4DT/hI4Xg=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=fZlD6vf1jso3iJ1nIMhzH+KTM14UhDBnSehn2AvNRiVFP1dJoc9UTh6uYskLq36eFalnUTP/ZE6DjpQzefpy7MWptVimRAcuM+npAC3WNxktZViM5dVfX2N290EwYau7oBCbI6BAY2BO0CvkbGhKa40Ib4pFGNluVIZUoSpgRh0= ARC-Authentication-Results:i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=lI0ofhJ7; arc=fail smtp.client-ip=40.107.201.62 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="lI0ofhJ7" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=aYaszVB2r10xljXKYJg7UTMCebVe9VRLqp9QfGK4elTfEia6UPMueaGQRMgdZGmTHwPlYIT+HWfXJd3ZyvTnZbh/1QBOQYXpndKryYCZ7OazDZwQqV7HwLUtWLxIsVRK6N3nptNAb33KSoFJXDNtb8Q9AaErfpQlScjcHrEcG9sHvDEvzL4KEnEIdRj1RQrgFJu7KPZxFipcLpeUyD33uOANcLHsbHfbRAvgv5Ky9O8yM6VCoaLfQrvj1WYSLpqviE7PmhzKs7qzg1KHA+yCUj1FE37sYkl/vVWAN+m4z4Y+E5SwRZV82Xsi9jI+nXgLR+YR0Tn/D9TKGvBEwsT0PQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=H0OD0yhS6PLeQOLUP2bdroMsBPBejqn+PC8aM32GKR4=; b=uEnPB+2Wm7P5PHyhDITEEre+TUd0OAf7AKQAPJ9dMTBJy2aGF4n7m/pWjy3qNKRhGOFbdvlg7QUTeTAFa3o6eEf2H3Afxdw+kwD7mOx43pwsfdWWqMcKqDZZJXv/CxCyQGGIiiEHQJw3O2iLTJSTCc/WV9D9it77UKeI+Ov2FNYBZA4RW7JcIycbJ51cb9+2edolWX+NjLs9si0yxgjznVIPkimxs2bkEIqisRz7VvqPKCrg//jhRJIlFBcMspJV6vnnsAhgXGWI86S7QaVujAqFPb7Yd1WzhynEKwGkwh5dNx1ht6s4wsQMv0J7b0kS0oPEVGo3HSpfY/6qhNxx0g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=H0OD0yhS6PLeQOLUP2bdroMsBPBejqn+PC8aM32GKR4=; b=lI0ofhJ7Mc7UPsWhDuGDRv2pdqCEMAIUg6LWAmbHl541fg5h8wBfQlCrNsM0vxJaW981DNkkIgTS1Ayjac8qFgq4YbSpRVpoRBr1Zb17G+JxCcC9au+KPDkZ3vL/nY9h14r4hvpSgYwEsk7dMJhL6mNk6DMAEVBJgcgv+TfcPXM= Received: from BL1P222CA0005.NAMP222.PROD.OUTLOOK.COM (2603:10b6:208:2c7::10) by DS0PR12MB8069.namprd12.prod.outlook.com (2603:10b6:8:f0::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9520.6; Fri, 16 Jan 2026 09:43:29 +0000 Received: from BN3PEPF0000B06D.namprd21.prod.outlook.com (2603:10b6:208:2c7:cafe::4d) by BL1P222CA0005.outlook.office365.com (2603:10b6:208:2c7::10) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9499.7 via Frontend Transport; Fri, 16 Jan 2026 09:43:29 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by BN3PEPF0000B06D.mail.protection.outlook.com (10.167.243.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9542.0 via Frontend Transport; Fri, 16 Jan 2026 09:43:29 +0000 Received: from satlexmb08.amd.com (10.181.42.217) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 16 Jan 2026 03:43:29 -0600 Received: from [10.136.34.241] (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Fri, 16 Jan 2026 03:43:25 -0600 Message-ID: <95f2091c-273e-4e36-b543-735748efd5fc@amd.com> Date: Fri, 16 Jan 2026 15:13:24 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] sched/clock: Avoid false sharing for sched_clock_irqtime To: Wangyang Guo , Peter Zijlstra , Vincent Guittot CC: Ingo Molnar , Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , , Shrikanth Hegde , Benjamin Lei , Tim Chen , Tianyou Li References: <20260116023945.1849329-1-wangyang.guo@intel.com> Content-Language: en-US From: K Prateek Nayak In-Reply-To: <20260116023945.1849329-1-wangyang.guo@intel.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B06D:EE_|DS0PR12MB8069:EE_ X-MS-Office365-Filtering-Correlation-Id: bc397819-c5f2-434e-5dde-08de54e3b495 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?utf-8?B?NXJiTFhTSWhhWWNxdW1HRXkxZ3kyajlGeDFtMERNOXNMTEh3K002OE5sV0Y4?= =?utf-8?B?V1JOYVZFQzBvUGdKdUFJVGQ0V0J1cGc1UHRtbWEvQ1NRL05ZbkdSYTdnTnBo?= =?utf-8?B?VVFjZWJ6dkJOdWwwS0JNRXdxeElxTy9GK1QwY0Y1WUlPMXVTam90b0lqSXY1?= =?utf-8?B?SVZHbFdOSytMYWJVYlNsbFpOWGNGMzVhL1VyTVRFVGhnS0xKOUVrcXdvZDRM?= =?utf-8?B?emdHdHRsWVF4Y2VBZ0Vaa2MxZ1VzZ3ZSUTVqQU1wZWVUMXRSQWVsTTRCRDZy?= =?utf-8?B?MVdNK2hRTk9SVFJBNnBvT3NuZlF6TE5SdlNkbWRVdXRrV1JKQ0k0V1RvckRz?= =?utf-8?B?SU1PZzQ1TldEOXQ5d2F1ZGFSYm1MdnNpMEJrRS8wRzdFcE9aaFJLM29NNk8w?= =?utf-8?B?U3ZkNWxZY1cvazFFNG9rVzE3eGRhME9LTUVxc1lKN0JvaWRNcWtLclp6SkJa?= =?utf-8?B?U3JXSmZ4N0FlemJpYVlObDA1WGpvYlNuUldzZnNQemFVMk5JSkJNRG9ZeXh0?= =?utf-8?B?Z3FWbVRWb3R4WVZ2Ym9HTE03T1JhMk1lQ2Zsejc5MEFmRTBZUFEyaGxqSnZX?= =?utf-8?B?UG9jZHRMbk9QVTNlUE0rNlB0ZWZlU0tvbklJaGRMNWR5TmtxUHZNNjROWVVP?= =?utf-8?B?RzNOWmpwUXVPK3FTeUpIK3djUnJ1MUFralUrTUJPS3NvcXNGRW5kSXRiY2Mv?= =?utf-8?B?Ym1ydi84bmNISmFVQzlOcjkrNlNpTTJiczhnUXYvMzNQNVp4TERISWk0aFdH?= =?utf-8?B?eEpMNFg1dlJpNGdoK2c1VDkwRU9hcXpHNmtFUEhHZGh0L3ZIWWVEM1l3RmlT?= =?utf-8?B?MStjK1lNSEoxZzIrTkYwdHJoMUV3N2xLMGUyVXJ2cGMxeWNWSGZLT3RRTVRW?= =?utf-8?B?WUFWbytIR2VqS3VUZXpWemlzc3oxVmkwRWNLWEt1T0taYWt4WUlqajRDZHBS?= =?utf-8?B?VGRpS2M2ZmxGUlJLYmtsUVdLb0hmZ3luOXIxS2hvNHFDUlZ3RW1xTThKUXpk?= =?utf-8?B?dnRvM1ZLWnlQR3p6TWhsVXNhaFVqU1Z6d3FPME9zU3JZc2RwRitFOExNREtI?= =?utf-8?B?bkFPamJTb1J1Y01wbWg1YlU3eDFvVmdldDBBZGtML2UxZFV3TDYrdFA2SFN6?= =?utf-8?B?QUpxa2FpY0M5MEEyK1RxajhYZkRkc3FVaFNuZ1lLRWQxSmt1d210ODQxTWJC?= =?utf-8?B?emgwYTZzd3lKV2hWQUorRC9TQ0FpRVFOUi9qUW1EanRDRUs0d2MxSlBlUTN2?= =?utf-8?B?Vk1ncWxCOXZtSjBBd1MrZTdyekRGWWp5Q1dxRndhb2dteFI3M2lSL1JDT0tv?= =?utf-8?B?NlF4WkE4ZVliUVdiOURMeUhDR1oySVlMb0dPMTl6bktLVEtQK2tNdDQ3czEz?= =?utf-8?B?VXJhTlVWcFh0S1dyYTV6ODlZRTlBTWN2bkFoZEYwdVdiYW1wY3Z3ZWh1UUdN?= =?utf-8?B?Si9OejM4MCsyOHVOMnR2djcvUWROalBDQ1lpZHRKazNrUWJtVmFUNUR4K1pr?= =?utf-8?B?R3k0dXFJOXJVTUZWd1dlK001QzJ1N2VGeFVUMEFmemo3SWFnaDlaUXpvbEY0?= =?utf-8?B?elczOWVsTmViY0pnMW80b1JPRVZBMXJ5M21WZjVOVDBOODlCekt1MHU4R3RL?= =?utf-8?B?NGlkdVdSYklTMjQxemdralp4aVNtb2dia1NsSEgwR2pCa2dqR1ZwRGlCenM5?= =?utf-8?B?cmJSdjFKTDNkejN5R2x6ZGZEbWZ6WklQMFZ6RGo2VGdFVkhwVCsybXNYUENB?= =?utf-8?B?YU52emxVSm5DOWJwY0JaMFlETm1RM25tOGJnVGNRdEo3T1lnK2lnSjI4VmU3?= =?utf-8?B?Zi9KQkM5c2JGK2ZNd0xnYWFPcTFEZU5wY2pEQnpjU2RNMVdIZEZmT2lUR3M0?= =?utf-8?B?SmlIenorOGlvNHNXRUdMU05weDlKTkF2eUErRXU5WmM4KzBvSVRNaGRhRUxE?= =?utf-8?B?ZlVUZWVvSEVVN1Q3UG1KZnhKcCt4dXRqbGlMR2lTcEdvRm4zVHJvdVgvb1I0?= =?utf-8?B?WlJJeTNsdE5OcTMrVTJxanI2Sm5BVndKNTI2ZnA3bzZnMjV6NWJtalRncGNq?= =?utf-8?B?ZE1wOHk4dm5KajRoUHJSakFjMHZqQklWcEkycldsN3EySjlaUTBCRkRQZzY1?= =?utf-8?B?bnFmd2pqMW9WMkpzZEVibmQxanBEeVlUZzZpOE1hMXhnYlpaSmlCa3FnNEFV?= =?utf-8?B?VmVHMXdLbVVWZnRubEpwYW02WWttM2V6WGFpOERwYWFvN3lzbEF3eGU0WThC?= =?utf-8?B?UlBiVG4xL21aQUtCVXNPZS9BTFh3PT0=?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2026 09:43:29.6738 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc397819-c5f2-434e-5dde-08de54e3b495 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B06D.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8069 Hello Wangyang, On 1/16/2026 8:09 AM, Wangyang Guo wrote: > */ > DEFINE_PER_CPU(struct irqtime, cpu_irqtime); > > -int sched_clock_irqtime; > - > void enable_sched_clock_irqtime(void) > { > - sched_clock_irqtime = 1; > + static_branch_enable(&sched_clock_irqtime); > } > > +static void __disable_sched_clock_irqtime(struct work_struct *work) > +{ > + static_branch_disable(&sched_clock_irqtime); > +} > + > +static DECLARE_WORK(sched_clock_irqtime_work, __disable_sched_clock_irqtime); > + > void disable_sched_clock_irqtime(void) > { > - sched_clock_irqtime = 0; > + /* disable_sched_clock_irqtime can be called in atomic > + * context with mark_tsc_unstable(), use wq to avoid > + * "sleeping in atomic context" warning. > + */ > + if (irqtime_enabled()) > + schedule_work(&sched_clock_irqtime_work); > } Your approach looks good to avoid the scheduling while atomic issue. Just a small observation: The only user of disable_sched_clock_irqtime() is tsc_.*mark_unstable() which calls clear_sched_clock_stable() just before doing disable_sched_clock_irqtime(). It makes me wonder if we can just reuse "sched_clock_work" to also\ disable sched_clock_irqtime()? Peter, Vincent, do we need to do enable_sched_clock_irqtime() that early when we detect TSC freq / sched_clock_register() or can we wait until we do __set_sched_clock_stable()? If we can wait until we mark sched_clock() as stable, we can consolidate enabling / disabling of irqtime with that of __sched_clock_stable. Something like the following on top of Wangyang's patch: diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 7d3e13e14eab..8bb9c0baa93d 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1143,7 +1143,6 @@ static void tsc_cs_mark_unstable(struct clocksource *cs) tsc_unstable = 1; if (using_native_sched_clock()) clear_sched_clock_stable(); - disable_sched_clock_irqtime(); pr_info("Marking TSC unstable due to clocksource watchdog\n"); } @@ -1213,7 +1212,6 @@ void mark_tsc_unstable(char *reason) tsc_unstable = 1; if (using_native_sched_clock()) clear_sched_clock_stable(); - disable_sched_clock_irqtime(); pr_info("Marking TSC unstable due to %s\n", reason); clocksource_mark_unstable(&clocksource_tsc_early); @@ -1234,6 +1232,22 @@ bool tsc_clocksource_watchdog_disabled(void) tsc_as_watchdog && !no_tsc_watchdog; } +#ifdef CONFIG_IRQ_TIME_ACCOUNTING +/* + * Allow IRQ time accounting if the user hasn't + * disabled it and TSC is found to be stable at + * the time of late_initcall(). + * + * If the TSC is detected to be unstable later, + * the IRQ time accounting will be disabled from + * clear_sched_clock_stable(). + */ +bool sched_clock_supports_irqtime_acct(void) +{ + return !no_sched_irq_time && !tsc_unstable; +} +#endif + static void __init check_system_tsc_reliable(void) { #if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC) @@ -1551,9 +1565,6 @@ void __init tsc_init(void) cyc2ns_init_secondary_cpus(); - if (!no_sched_irq_time) - enable_sched_clock_irqtime(); - lpj_fine = get_loops_per_jiffy(); check_system_tsc_reliable(); diff --git a/include/linux/sched/clock.h b/include/linux/sched/clock.h index 196f0ca351a2..e9b8c88fada5 100644 --- a/include/linux/sched/clock.h +++ b/include/linux/sched/clock.h @@ -104,11 +104,7 @@ extern u64 local_clock(void); * The reason for this explicit opt-in is not to have perf penalty with * slow sched_clocks. */ -extern void enable_sched_clock_irqtime(void); -extern void disable_sched_clock_irqtime(void); -#else -static inline void enable_sched_clock_irqtime(void) {} -static inline void disable_sched_clock_irqtime(void) {} +bool sched_clock_supports_irqtime_acct(void); #endif #endif /* _LINUX_SCHED_CLOCK_H */ diff --git a/kernel/sched/clock.c b/kernel/sched/clock.c index f5e6dd6a6b3a..4d43eef8c326 100644 --- a/kernel/sched/clock.c +++ b/kernel/sched/clock.c @@ -137,6 +137,8 @@ notrace static void __set_sched_clock_stable(void) scd->tick_gtod, __gtod_offset, scd->tick_raw, __sched_clock_offset); + if (sched_clock_supports_irqtime_acct()) + enable_sched_clock_irqtime(); static_branch_enable(&__sched_clock_stable); tick_dep_clear(TICK_DEP_BIT_CLOCK_UNSTABLE); } @@ -173,6 +175,7 @@ notrace static void __sched_clock_work(struct work_struct *work) scd->tick_gtod, __gtod_offset, scd->tick_raw, __sched_clock_offset); + disable_sched_clock_irqtime(); static_branch_disable(&__sched_clock_stable); } diff --git a/kernel/sched/cputime.c b/kernel/sched/cputime.c index a5a8bd0a5ede..83dd9f299ee4 100644 --- a/kernel/sched/cputime.c +++ b/kernel/sched/cputime.c @@ -32,21 +32,9 @@ void enable_sched_clock_irqtime(void) static_branch_enable(&sched_clock_irqtime); } -static void __disable_sched_clock_irqtime(struct work_struct *work) -{ - static_branch_disable(&sched_clock_irqtime); -} - -static DECLARE_WORK(sched_clock_irqtime_work, __disable_sched_clock_irqtime); - void disable_sched_clock_irqtime(void) { - /* disable_sched_clock_irqtime can be called in atomic - * context with mark_tsc_unstable(), use wq to avoid - * "sleeping in atomic context" warning. - */ - if (irqtime_enabled()) - schedule_work(&sched_clock_irqtime_work); + static_branch_disable(&sched_clock_irqtime); } static void irqtime_account_delta(struct irqtime *irqtime, u64 delta, diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 164ebf47e5fd..3bae8baf7c00 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -3333,6 +3333,8 @@ static inline u64 irq_time_read(int cpu) return total; } +void enable_sched_clock_irqtime(void); +void disable_sched_clock_irqtime(void); #else /* !CONFIG_IRQ_TIME_ACCOUNTING: */ static inline int irqtime_enabled(void) @@ -3340,6 +3342,13 @@ static inline int irqtime_enabled(void) return 0; } +static inline bool sched_clock_supports_irqtime_acct(void) +{ + return false; +} + +static inline void enable_sched_clock_irqtime(void) {} +static inline void disable_sched_clock_irqtime(void) {} #endif /* !CONFIG_IRQ_TIME_ACCOUNTING */ #ifdef CONFIG_CPU_FREQ diff --git a/kernel/time/sched_clock.c b/kernel/time/sched_clock.c index f39111830ca3..1cdd10026279 100644 --- a/kernel/time/sched_clock.c +++ b/kernel/time/sched_clock.c @@ -174,6 +174,18 @@ static enum hrtimer_restart sched_clock_poll(struct hrtimer *hrt) return HRTIMER_RESTART; } +#ifdef CONFIG_IRQ_TIME_ACCOUNTING +/* + * Enable IRQ time accounting if we have a fast enough sched_clock(). + * This is checked as a part of late_initcall() once all the clock + * devices have registered themselves. + */ +bool sched_clock_supports_irqtime_acct(void) +{ + return irqtime > 0 || (irqtime == -1 && cd.rate >= 1000000); +} +#endif + void sched_clock_register(u64 (*read)(void), int bits, unsigned long rate) { u64 res, wrap, new_mask, new_epoch, cyc, ns; @@ -238,10 +250,6 @@ void sched_clock_register(u64 (*read)(void), int bits, unsigned long rate) pr_info("sched_clock: %u bits at %lu%cHz, resolution %lluns, wraps every %lluns\n", bits, r, r_unit, res, wrap); - /* Enable IRQ time accounting if we have a fast enough sched_clock() */ - if (irqtime > 0 || (irqtime == -1 && rate >= 1000000)) - enable_sched_clock_irqtime(); - local_irq_restore(flags); pr_debug("Registered %pS as sched_clock source\n", read); --- I don't know if it is any better (or even correct) but it does reduce the scope of {enable,disable}_sched_clock_irqtime() to kernel/sched/. Thoughts? -- Thanks and Regards, Prateek