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Thu, 21 Aug 2025 12:06:55 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEALjqD+64g6+aUDcHQDd+nzuWWoTg3zL905SlfzVM/ab/dThtX7+FD2an4jIMQPPN/oJHtgg== X-Received: by 2002:a17:902:db10:b0:243:e3:a4e5 with SMTP id d9443c01a7336-2462ef94f72mr4596425ad.48.1755803215088; Thu, 21 Aug 2025 12:06:55 -0700 (PDT) Received: from [192.168.1.6] ([106.222.235.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed50129dsm62047125ad.129.2025.08.21.12.06.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Aug 2025 12:06:54 -0700 (PDT) Message-ID: <95fed1b1-8359-4221-8245-dc12335dc4b6@oss.qualcomm.com> Date: Fri, 22 Aug 2025 00:36:47 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/6] arm64: dts: qcom: sa8775p: Add gpu and gmu nodes To: Dmitry Baryshkov Cc: Gaurav Kohli , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Puranam V G Tejaswi , Sean Paul , Konrad Dybcio , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Connor Abbott , Srinivas Kandagatla , Rob Clark References: <20250822-a663-gpu-support-v4-0-97d26bb2144e@oss.qualcomm.com> <20250822-a663-gpu-support-v4-3-97d26bb2144e@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: <20250822-a663-gpu-support-v4-3-97d26bb2144e@oss.qualcomm.com> Content-Type: text/plain; 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As of now all > SKUs have the same GPU fmax, so there is no requirement of > speed bin support. > > Signed-off-by: Puranam V G Tejaswi > Signed-off-by: Akhil P Oommen > Reviewed-by: Dmitry Baryshkov Dmitry, FYI, I retained your R-b tag. -Akhil > --- > arch/arm64/boot/dts/qcom/lemans.dtsi | 116 +++++++++++++++++++++++++++++++++++ > 1 file changed, 116 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi > index 8ceb59742a9fc6562b2c38731ddabe3a549f7f35..8eac8d4719db9230105ad93ac22287850b6b007c 100644 > --- a/arch/arm64/boot/dts/qcom/lemans.dtsi > +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi > @@ -1097,6 +1097,18 @@ ipcc: mailbox@408000 { > #mbox-cells = <2>; > }; > > + qfprom: efuse@784000 { > + compatible = "qcom,sa8775p-qfprom", "qcom,qfprom"; > + reg = <0x0 0x00784000 0x0 0x2410>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + gpu_speed_bin: gpu_speed_bin@240c { > + reg = <0x240c 0x1>; > + bits = <0 8>; > + }; > + }; > + > gpi_dma2: dma-controller@800000 { > compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; > reg = <0x0 0x00800000 0x0 0x60000>; > @@ -4093,6 +4105,110 @@ tcsr: syscon@1fc0000 { > reg = <0x0 0x1fc0000 0x0 0x30000>; > }; > > + gpu: gpu@3d00000 { > + compatible = "qcom,adreno-663.0", "qcom,adreno"; > + reg = <0x0 0x03d00000 0x0 0x40000>, > + <0x0 0x03d9e000 0x0 0x1000>, > + <0x0 0x03d61000 0x0 0x800>; > + reg-names = "kgsl_3d0_reg_memory", > + "cx_mem", > + "cx_dbgc"; > + interrupts = ; > + iommus = <&adreno_smmu 0 0xc00>, > + <&adreno_smmu 1 0xc00>; > + operating-points-v2 = <&gpu_opp_table>; > + qcom,gmu = <&gmu>; > + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "gfx-mem"; > + #cooling-cells = <2>; > + > + status = "disabled"; > + > + gpu_zap_shader: zap-shader { > + memory-region = <&pil_gpu_mem>; > + }; > + > + gpu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-405000000 { > + opp-hz = /bits/ 64 <405000000>; > + opp-level = ; > + opp-peak-kBps = <5285156>; > + opp-supported-hw = <0x3>; > + }; > + > + opp-530000000 { > + opp-hz = /bits/ 64 <530000000>; > + opp-level = ; > + opp-peak-kBps = <12484375>; > + opp-supported-hw = <0x2>; > + }; > + > + opp-676000000 { > + opp-hz = /bits/ 64 <676000000>; > + opp-level = ; > + opp-peak-kBps = <8171875>; > + opp-supported-hw = <0x1>; > + }; > + > + opp-778000000 { > + opp-hz = /bits/ 64 <778000000>; > + opp-level = ; > + opp-peak-kBps = <10687500>; > + opp-supported-hw = <0x1>; > + }; > + > + opp-800000000 { > + opp-hz = /bits/ 64 <800000000>; > + opp-level = ; > + opp-peak-kBps = <12484375>; > + opp-supported-hw = <0x1>; > + }; > + }; > + }; > + > + gmu: gmu@3d6a000 { > + compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu"; > + reg = <0x0 0x03d6a000 0x0 0x34000>, > + <0x0 0x03de0000 0x0 0x10000>, > + <0x0 0x0b290000 0x0 0x10000>; > + reg-names = "gmu", "rscc", "gmu_pdc"; > + interrupts = , > + ; > + interrupt-names = "hfi", "gmu"; > + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, > + <&gpucc GPU_CC_CXO_CLK>, > + <&gcc GCC_DDRSS_GPU_AXI_CLK>, > + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, > + <&gpucc GPU_CC_AHB_CLK>, > + <&gpucc GPU_CC_HUB_CX_INT_CLK>, > + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; > + clock-names = "gmu", > + "cxo", > + "axi", > + "memnoc", > + "ahb", > + "hub", > + "smmu_vote"; > + power-domains = <&gpucc GPU_CC_CX_GDSC>, > + <&gpucc GPU_CC_GX_GDSC>; > + power-domain-names = "cx", > + "gx"; > + iommus = <&adreno_smmu 5 0xc00>; > + operating-points-v2 = <&gmu_opp_table>; > + > + gmu_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + opp-level = ; > + }; > + }; > + }; > + > gpucc: clock-controller@3d90000 { > compatible = "qcom,sa8775p-gpucc"; > reg = <0x0 0x03d90000 0x0 0xa000>; >