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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id n19-20020a05600c4f9300b003a83ca67f73sm93592wmq.3.2022.11.10.08.29.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Nov 2022 08:29:43 -0800 (PST) Message-ID: <9600a696-c3dd-acc5-3489-569c1590f224@sifive.com> Date: Thu, 10 Nov 2022 16:29:42 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.1 Subject: Re: [PATCH v6 10/10] pwm: dwc: use clock rate in hz to avoid rounding issues Content-Language: en-GB To: =?UTF-8?Q?Uwe_Kleine-K=c3=b6nig?= Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha References: <20221020151610.59443-1-ben.dooks@sifive.com> <20221020151610.59443-11-ben.dooks@sifive.com> <20221110154214.pnv7rqsftomhqvmk@pengutronix.de> From: Ben Dooks In-Reply-To: <20221110154214.pnv7rqsftomhqvmk@pengutronix.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/11/2022 15:42, Uwe Kleine-König wrote: > Hello Ben, > > On Thu, Oct 20, 2022 at 04:16:10PM +0100, Ben Dooks wrote: >> As noted, the clock-rate when not a nice multiple of ns is probably >> going to end up with inacurate caculations, as well as on a non pci >> system the rate may change (although we've not put a clock rate >> change notifier in this code yet) so we also add some quick checks >> of the rate when we do any calculations with it. >> >> Signed-off-by; Ben Dooks >> Reported-by: Uwe Kleine-König >> --- >> drivers/pwm/pwm-dwc-of.c | 2 +- >> drivers/pwm/pwm-dwc.c | 29 ++++++++++++++++++++--------- >> drivers/pwm/pwm-dwc.h | 2 +- >> 3 files changed, 22 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c >> index c5b4351cc7b0..5f7f066859d4 100644 >> --- a/drivers/pwm/pwm-dwc-of.c >> +++ b/drivers/pwm/pwm-dwc-of.c >> @@ -50,7 +50,7 @@ static int dwc_pwm_plat_probe(struct platform_device *pdev) >> return dev_err_probe(dev, PTR_ERR(dwc->clk), >> "failed to get timer clock\n"); >> >> - dwc->clk_ns = NSEC_PER_SEC / clk_get_rate(dwc->clk); >> + dwc->clk_rate = clk_get_rate(dwc->clk); > > Given that clk_ns is introduced only in this series, I suggest to make > it right from the start. I was trying to keep the splitting of the driver and the clock changes separate to make any possible bisection easier. -- Ben