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Thu, 8 Sep 2022 06:38:33 GMT Received: from [10.216.34.143] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 7 Sep 2022 23:38:26 -0700 Message-ID: <9609ade9-da03-6c3e-4d1a-80e97ac3b692@quicinc.com> Date: Thu, 8 Sep 2022 12:08:23 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH v3 3/3] arm64: dts: qcom: sc7280: Add missing aggre0, aggre1 clocks Content-Language: en-US To: Krzysztof Kozlowski , CC: , , , , , , , , , , , , Andy Gross , Bjorn Andersson , "Rob Herring" , Krzysztof Kozlowski , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" References: <1662171184-25211-1-git-send-email-quic_krichai@quicinc.com> <1662171184-25211-4-git-send-email-quic_krichai@quicinc.com> From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 9tovZ1LiDMIuOSwd9RYarpfoggFYj1RV X-Proofpoint-ORIG-GUID: 9tovZ1LiDMIuOSwd9RYarpfoggFYj1RV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-08_04,2022-09-07_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2209080023 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/7/2022 5:52 PM, Krzysztof Kozlowski wrote: > On 03/09/2022 04:13, Krishna chaitanya chundru wrote: >> Add missing aggre0, aggre1 clocks. >> >> Signed-off-by: Krishna chaitanya chundru >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index e66fc67..a5ce095 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -2043,6 +2043,8 @@ >> <&gcc GCC_PCIE_1_SLV_AXI_CLK>, >> <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, >> <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, >> + <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, >> + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, >> <&gcc GCC_DDRSS_PCIE_SF_CLK>; >> >> clock-names = "pipe", >> @@ -2055,6 +2057,8 @@ >> "bus_slave", >> "slave_q2a", >> "tbu", >> + "aggre0", >> + "aggre1", >> "ddrss_sf_tbu"; >> > Same as binding - adding entries in the middle causes ABI issues. > > Best regards, > Krzysztof Ok I will change the order as suggested.