From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752686AbdHVUps (ORCPT ); Tue, 22 Aug 2017 16:45:48 -0400 Received: from us01smtprelay-2.synopsys.com ([198.182.60.111]:34846 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752477AbdHVUpr (ORCPT ); Tue, 22 Aug 2017 16:45:47 -0400 Subject: Re: [PATCH 3/5] ARC: AXS103: DTS: Add core pll node to manage cpu frequency To: Eugeniy Paltsev , "linux-snps-arc@lists.infradead.org" CC: "linux-kernel@vger.kernel.org" , "Alexey Brodkin" , Rob Herring , "Mark Rutland" , "devicetree@vger.kernel.org" References: <20170814161213.17522-1-Eugeniy.Paltsev@synopsys.com> <20170814161213.17522-4-Eugeniy.Paltsev@synopsys.com> From: Vineet Gupta Message-ID: <9624a76d-a31f-10fc-aec5-5ffa1d437c3d@synopsys.com> Date: Tue, 22 Aug 2017 13:45:28 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <20170814161213.17522-4-Eugeniy.Paltsev@synopsys.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [10.10.161.108] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote: > Add core pll node (core_clk) to manage cpu frequency. > core_clk represents pll itself. > input_clk represents clock signal source (basically xtal) which > comes to pll input. > > Signed-off-by: Eugeniy Paltsev > --- > arch/arc/boot/dts/axc003.dtsi | 11 +++++++++-- > arch/arc/boot/dts/axc003_idu.dtsi | 11 +++++++++-- > 2 files changed, 18 insertions(+), 4 deletions(-) > > diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi > index cc9239e..dca7e39 100644 > --- a/arch/arc/boot/dts/axc003.dtsi > +++ b/arch/arc/boot/dts/axc003.dtsi > @@ -24,10 +24,17 @@ > > ranges = <0x00000000 0x0 0xf0000000 0x10000000>; > > - core_clk: core_clk { > + input_clk: input-clk { > #clock-cells = <0>; > compatible = "fixed-clock"; > - clock-frequency = <90000000>; > + clock-frequency = <33333333>; > + }; > + > + core_clk: core-clk@80 { > + compatible = "snps,axs10x-arc-pll-clock"; > + reg = <0x80 0x10>, <0x100 0x10>; > + #clock-cells = <0>; > + clocks = <&input_clk>; > }; > > core_intc: archs-intc@cpu { > diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi > index 4ebb2170..5b56bef 100644 > --- a/arch/arc/boot/dts/axc003_idu.dtsi > +++ b/arch/arc/boot/dts/axc003_idu.dtsi > @@ -24,10 +24,17 @@ > > ranges = <0x00000000 0x0 0xf0000000 0x10000000>; > > - core_clk: core_clk { > + input_clk: input-clk { > #clock-cells = <0>; > compatible = "fixed-clock"; > - clock-frequency = <100000000>; > + clock-frequency = <33333333>; > + }; > + > + core_clk: core-clk@80 { > + compatible = "snps,axs10x-arc-pll-clock"; > + reg = <0x80 0x10>, <0x100 0x10>; > + #clock-cells = <0>; > + clocks = <&input_clk>; > }; > > core_intc: archs-intc@cpu { Do we have a bisectability issue here - isn't system broken temporarily at 2/5 - and only 3/5 makes it work again - if so we need to squash them together ! -Vineet