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Fri, 13 Dec 2024 16:37:12 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BDGbBsK005589 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 Dec 2024 16:37:11 GMT Received: from [10.226.59.182] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 13 Dec 2024 08:37:10 -0800 Message-ID: <96368cf8-792b-598c-0c82-e6d2f46cfb74@quicinc.com> Date: Fri, 13 Dec 2024 09:37:09 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.0 Subject: Re: [PATCH V2 3/8] accel/amdxdna: Add RyzenAI-npu6 support Content-Language: en-US To: Lizhi Hou , , CC: , , , , , , Xiaoming Ren References: <20241206220001.164049-1-lizhi.hou@amd.com> <20241206220001.164049-4-lizhi.hou@amd.com> From: Jeffrey Hugo In-Reply-To: <20241206220001.164049-4-lizhi.hou@amd.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: pkU0pjHH5yyIHcWVA9wJi3r_NfJz-CZu X-Proofpoint-GUID: pkU0pjHH5yyIHcWVA9wJi3r_NfJz-CZu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 priorityscore=1501 spamscore=0 mlxlogscore=712 impostorscore=0 suspectscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412130117 On 12/6/2024 2:59 PM, Lizhi Hou wrote: > Add NPU6 registers and other private configurations. > > Co-developed-by: Xiaoming Ren > Signed-off-by: Xiaoming Ren > Signed-off-by: Lizhi Hou > --- > drivers/accel/amdxdna/Makefile | 3 +- > drivers/accel/amdxdna/npu6_regs.c | 121 ++++++++++++++++++++++++++++++ This looks like dead code to me. I would expect somewhere else in the driver, dev_npu6_info would be used, but that is not the case. What am I missing? -Jeff