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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id a8-20020a05651c010800b0026c3975f488sm1479001ljb.26.2022.09.23.10.49.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 Sep 2022 10:49:22 -0700 (PDT) Message-ID: <966b46f5-ed3b-9daa-4cfb-602a534a8bfc@linaro.org> Date: Fri, 23 Sep 2022 19:49:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCHv2 1/3] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Content-Language: en-US To: Dinh Nguyen , jh80.chung@samsung.com Cc: ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20220922220308.609422-1-dinguyen@kernel.org> <20220922220308.609422-2-dinguyen@kernel.org> From: Krzysztof Kozlowski In-Reply-To: <20220922220308.609422-2-dinguyen@kernel.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/09/2022 00:03, Dinh Nguyen wrote: > Document the optional "altr,sysmgr-syscon" binding that is used to > access the System Manager register that controls the SDMMC clock > phase. > > Signed-off-by: Dinh Nguyen Thank you for your patch. There is something to discuss/improve. > --- > v2: added > --- > .../devicetree/bindings/mmc/synopsys-dw-mshc.yaml | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml > index ae6d6fca79e2..aece6a337262 100644 > --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml > +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml > @@ -38,6 +38,18 @@ properties: > - const: biu > - const: ciu > > + altr,sysmgr-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle to the sysmgr node > + - description: register offset that controls the SDMMC clock phase > + description: > + Contains the phandle to System Manager block that contains > + the SDMMC clock-phase control register. The first value is the pointer > + to the sysmgr and the 2nd value is the register offset for the SDMMC > + clock phase register. You need to restrict it per variant (altera). Move the allOf from top of the file to place above unevaluatedProperties and add if:then: making it false for other variants. Best regards, Krzysztof