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Miller" , Eric Dumazet , Paolo Abeni , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Maxime Chevallier , Heiner Kallweit , Russell King , David Wu , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_net-next_v10_1/6=5D_dt-bindings=3A_?= =?US-ASCII?Q?net=3A_pcs=3A_add_rockchip=2Crk3568-xpcs_support?= User-Agent: K-9 Mail for Android In-Reply-To: <20261006132428.GA1659963-robh@kernel.org> References: <20261005223011.1124347-1-coiaprant@gmail.com> <20261005223011.1124347-2-coiaprant@gmail.com> <20261006132428.GA1659963-robh@kernel.org> Message-ID: <96FA84EA-3C0E-4FAC-963F-2A8165538748@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On October 6, 2026 9:24:28 PM GMT+08:00, Rob Herring wr= ote: >On Tue, Oct 06, 2026 at 06:30:03AM +0800, Coia Prant wrote: >> Add device tree binding documentation for the Synopsys DesignWare >> XPCS integrated on the Rockchip RK3568 SoC=2E >>=20 >> The XPCS is accessed over the APB3 bus and internally connected to >> a Naneng Combo SerDes PHY=2E It supports 1000BASE-X, SGMII, and >> QSGMII modes, with four MII ports=2E >>=20 >> The four MII ports are described as ethernet-pcs-mii@N child nodes, >> consumed by the Rockchip XPCS glue driver later in this series=2E >>=20 >> phys and phy-names are required because dtbs_check only validates >> required properties for enabled nodes=2E The SerDes link is a board-lev= el >> design choice (combphy1 on some boards, combphy2 on others), so these >> properties must be provided by the board device tree, not the SoC dtsi= =2E >>=20 >> The CRU reset lines (SRST_XPCS*) are intentionally not described: no >> in-tree user requests them, and bring-up relies on the PD_PIPE power >> domain, the SerDes PHY and the in-IP soft reset=2E They can be added >> later as optional without breaking ABI=2E >>=20 >> Signed-off-by: Coia Prant >> --- >> =2E=2E=2E/net/pcs/rockchip,rk3568-xpcs=2Eyaml | 110 ++++++++++= ++++++++ >> 1 file changed, 110 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/net/pcs/rockchip,= rk3568-xpcs=2Eyaml >>=20 >> diff --git a/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-= xpcs=2Eyaml b/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpc= s=2Eyaml >> new file mode 100644 >> index 0000000000000=2E=2E703fcff0e3f70 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/net/pcs/rockchip,rk3568-xpcs=2E= yaml >> @@ -0,0 +1,110 @@ >> +# SPDX-License-Identifier: (GPL-2=2E0-only OR BSD-2-Clause) >> +%YAML 1=2E2 >> +--- >> +$id: http://devicetree=2Eorg/schemas/net/pcs/rockchip,rk3568-xpcs=2Eya= ml# >> +$schema: http://devicetree=2Eorg/meta-schemas/core=2Eyaml# >> + >> +title: Rockchip RK3568 Synopsys DesignWare Ethernet PCS >> + >> +maintainers: >> + - Coia Prant >> + >> +description: | >> + Rockchip RK3568 SoC integrates a Synopsys DesignWare Ethernet Physic= al >> + Coding Sublayer (XPCS)=2E >> + The PCS provides an interface between the Media Access Control (MAC) >> + and the Physical Medium Attachment (PMA) sublayer through a Media >> + Independent Interface (GMII)=2E >> + >> + The XPCS is accessed over the APB3 bus and internally connected to a >> + Naneng Combo SerDes PHY=2E >> + It supports 1000BASE-X, SGMII and QSGMII modes=2E >> + >> + The block contains four MII ports that can be individually enabled a= nd >> + routed to one of the Ethernet GMAC controllers via the pcs-handle >> + property in the MAC device tree node=2E >> + >> +properties: >> + compatible: >> + const: rockchip,rk3568-xpcs >> + >> + reg: >> + maxItems: 1 >> + >> + "#address-cells": >> + const: 1 >> + >> + "#size-cells": >> + const: 0 >> + >> + clocks: >> + items: >> + - description: APB3 bus interface clock (clk_csr_i), required fo= r register access >> + - description: EEE clock (clk_eee_i), required for Energy Effici= ent Ethernet operation >> + >> + clock-names: >> + items: >> + - const: csr >> + - const: eee >> + >> + phys: >> + maxItems: 1 >> + >> + phy-names: >> + const: serdes > >You don't really need phy-names if there is only 1 entry=2E > >> + >> + power-domains: >> + maxItems: 1 >> + >> +patternProperties: >> + "^ethernet-pcs-mii@[0-3]$": >> + type: object >> + description: >> + One of the four MII ports of the XPCS=2E The port is linked to a= n >> + Ethernet MAC controller via the pcs-handle property in the MAC's >> + device tree node=2E >> + >> + properties: >> + reg: >> + description: MII port number=2E >> + enum: [0, 1, 2, 3] >> + >> + required: >> + - reg > >Why the child nodes? They don't contain anything=2E > >Perhaps that's due to pcs-handle not supporting arg cells to pass the=20 >port number? That's about to change[1]=2E > >Rob > >[1] https://github=2Ecom/devicetree-org/dt-schema/pull/198 Hi Rob, Both points make sense=2E 1=2E I'll drop phy-names since there's only a single entry=2E 2=2E For the ethernet-pcs-mii child nodes: you're right that they only contain 'reg'=2E The reason I used child nodes is because pcs-handle arg cells are not available yet -- PR #198 is still open and in RFC/change-request state=2E The RZN1 MII converter binding does the same thing: it declares MII ports as subnodes and references the PCS via pcs-handle, until arg cells land=2E So I'd like to keep the child nodes as a temporary workaround, and I'll add a note in the binding that this can be simplified once PR #198 is merged=2E Thanks, Coia