From: Jinjie Ruan <ruanjinjie@huawei.com>
To: Mark Rutland <mark.rutland@arm.com>,
<linux-arm-kernel@lists.infradead.org>
Cc: <ada.coupriediaz@arm.com>, <ardb@kernel.org>,
<catalin.marinas@arm.com>, <hca@linux.ibm.com>,
<linux-kernel@vger.kernel.org>, <maz@kernel.org>,
<peterz@infradead.org>, <vladimir.murzin@arm.com>,
<will@kernel.org>, <yang@os.amperecomputing.com>
Subject: Re: [RFC PATCH 01/13] arm64: preempt: Simplify and optimize __preempt_count_dec_and_test()
Date: Wed, 29 Jul 2026 11:56:56 +0800 [thread overview]
Message-ID: <96db4406-5000-49df-a9ef-b4e49eb206cd@huawei.com> (raw)
In-Reply-To: <20260728123859.2911495-2-mark.rutland@arm.com>
在 2026/7/28 20:38, Mark Rutland 写道:
> In arm64's __preempt_count_dec_and_test(), the final conditional load of
> 'ti->preempt_count' is always executed in the common case. The
> conditional load leads to unfortunate code generation for
> preempt_enable[_notrace](), and it would be better to unconditionally
> load 'ti->preempt_count', as described below.
>
> On arm64, struct thread_info contains the following union:
>
> | union {
> | u64 preempt_count;
> | struct {
> | u32 count;
> | u32 need_resched;
> | } preempt;
> | };
>
> Note: 'need_resched' is encoded so that '0' means a reschedule is
> needed, and '1' means a reschedule is NOT needed.
Indeed, that's true
>
> The core logic of __preempt_count_dec_and_test() is:
>
> | static inline bool __preempt_count_dec_and_test(void)
> | {
> | struct thread_info *ti = current_thread_info();
> | u64 pc = READ_ONCE(ti->preempt_count);
> |
> | WRITE_ONCE(ti->preempt.count, --pc);
> |
> | return !pc || !READ_ONCE(ti->preempt_count);
> | }
>
> The '!pc' condition can only be true when both:
>
> * The initial value of 'need_resched' was 0, meaning that a reschedule
> is needed. This should be rare.
At the moment of executing --pc, the probability of it coinciding with
the process needing scheduling is indeed very small.
>
> * The initial value of 'count' was exactly 1. This cannot be true for a
> nested preempt_disable() ... preempt_enable() sequence.
>
> Hence in common cases, '!pc' will be false, and it's necessary to
> execute the final READ_ONCE(ti->preempt_count).
>
> This results in a conditional branch in the common case, as can be seen
> when __preempt_count_dec_and_test() is outlined:
>
> | <outline___preempt_count_dec_and_test>:
> | mrs x2, sp_el0
> | ldr x1, [x2, #8]
> | mov w0, #0x1
> | sub x1, x1, #0x1
> | str w1, [x2, #8]
> | cbz x1, 1f
> | ldr x0, [x2, #8]
> | cmp x0, #0x0
> | cset w0, eq // eq = none
> | 1: ret
>
> It would be better to avoid the special case for 'pc == 0', and to
> always load 'ti->preempt_count' after decrementing 'ti->preempt.count'.
> For the common cases this will remove a conditional branch. For the rare
> cases where preemption is needed initially, this only adds a single
> load, whose cost should be dominated by other factors.
>
> Remove the special case for 'pc == 0', and always load the combined
> 'ti->preempt_count' after decrementing 'ti->preempt.count'.
>
> The removal of the conditional branch helps with code generation, as the
> compiler can more easily move a dependent slow path out-of-line, as
> demonstrated with the following compiled with GCC 15.2.0:
>
> | void outline_preempt_enable_notrace(void)
> | {
> | preempt_enable_notrace();
> | }
>
> Before this patch:
>
> | <outline_preempt_enable_notrace>:
> | mrs x1, sp_el0
> | ldr x0, [x1, #8]
> | sub x0, x0, #0x1
> | str w0, [x1, #8]
> | cbz x0, 1f
> | ldr x0, [x1, #8]
> | cbnz x0, 2f
> | 1: paciasp
> | stp x29, x30, [sp, #-16]!
> | mov x29, sp
> | bl preempt_schedule_notrace
> | ldp x29, x30, [sp], #16
> | autiasp
> | ret
> | 2: ret
>
> After this patch:
>
> | <outline_preempt_enable_notrace>:
> | mrs x0, sp_el0
> | ldr w1, [x0, #8]
> | sub w1, w1, #0x1
> | str w1, [x0, #8]
> | ldr x0, [x0, #8]
> | cbz x0, 1f
> | ret
> | 1: paciasp
> | stp x29, x30, [sp, #-16]!
> | mov x29, sp
> | bl preempt_schedule_notrace
> | ldp x29, x30, [sp], #16
> | autiasp
> | ret
>
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> Cc: Ada Couprie Diaz <ada.coupriediaz@arm.com>
> Cc: Ard Biesheuvel <ardb@kernel.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Jinjie Ruan <ruanjinjie@huawei.com>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Vladimir Murzin <vladimir.murzin@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Yang Shi <yang@os.amperecomputing.com>
> ---
> arch/arm64/include/asm/preempt.h | 29 +++++++++++------------------
> 1 file changed, 11 insertions(+), 18 deletions(-)
>
> diff --git a/arch/arm64/include/asm/preempt.h b/arch/arm64/include/asm/preempt.h
> index 932ea4b620428..ca2ad1a8db095 100644
> --- a/arch/arm64/include/asm/preempt.h
> +++ b/arch/arm64/include/asm/preempt.h
> @@ -55,30 +55,23 @@ static inline void __preempt_count_sub(int val)
> WRITE_ONCE(current_thread_info()->preempt.count, pc);
> }
>
> -static inline bool __preempt_count_dec_and_test(void)
> -{
> - struct thread_info *ti = current_thread_info();
> - u64 pc = READ_ONCE(ti->preempt_count);
> -
> - /* Update only the count field, leaving need_resched unchanged */
> - WRITE_ONCE(ti->preempt.count, --pc);
> -
> - /*
> - * If we wrote back all zeroes, then we're preemptible and in
> - * need of a reschedule. Otherwise, we need to reload the
> - * preempt_count in case the need_resched flag was cleared by an
> - * interrupt occurring between the non-atomic READ_ONCE/WRITE_ONCE
> - * pair.
> - */
> - return !pc || !READ_ONCE(ti->preempt_count);
> -}
> -
> static inline bool should_resched(int preempt_offset)
> {
> u64 pc = READ_ONCE(current_thread_info()->preempt_count);
> return pc == preempt_offset;
> }
>
> +static inline bool __preempt_count_dec_and_test(void)
> +{
> + /*
> + * We must load the combined 'prempt_count' after decrementing
> + * 'preempt.count' as an interrupt could modify 'need_resched' before
> + * __preempt_count_sub() writes back to 'preempt.count'.
> + */
> + __preempt_count_sub(1);
> + return should_resched(0);
In general, the functions are consistent.
Reviewed-by: Jinjie Ruan <ruanjinjie@huawei.com>
> +}
> +
> #ifdef CONFIG_PREEMPTION
>
> void preempt_schedule(void);
next prev parent reply other threads:[~2026-07-29 3:57 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-28 12:38 [RFC PATCH 00/13] arm64: Preemptible this_cpu_*() operations Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 01/13] arm64: preempt: Simplify and optimize __preempt_count_dec_and_test() Mark Rutland
2026-07-29 3:56 ` Jinjie Ruan [this message]
2026-07-28 12:38 ` [RFC PATCH 02/13] arm64: preempt: Treat should_resched() as unlikely Mark Rutland
2026-07-29 4:00 ` Jinjie Ruan
2026-07-28 12:38 ` [RFC PATCH 03/13] arm64: ptrace: Always inline pt_regs_[read,write}_reg() Mark Rutland
2026-07-29 4:02 ` Jinjie Ruan
2026-07-28 12:38 ` [RFC PATCH 04/13] arm64: percpu: Factor out percpu offset asm Mark Rutland
2026-07-29 4:03 ` Jinjie Ruan
2026-07-28 12:38 ` [RFC PATCH 05/13] arm64: gpr-num: Add wxN aliases for wN registers Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops Mark Rutland
2026-07-28 14:19 ` Peter Zijlstra
2026-07-28 14:30 ` Peter Zijlstra
2026-07-28 16:03 ` Mark Rutland
2026-07-28 16:49 ` Peter Zijlstra
2026-07-28 15:53 ` Mark Rutland
2026-07-28 16:46 ` Peter Zijlstra
2026-07-28 16:49 ` Peter Zijlstra
2026-08-04 13:23 ` Mark Rutland
2026-07-28 16:51 ` Heiko Carstens
2026-07-29 8:16 ` Heiko Carstens
2026-07-29 14:25 ` Vladimir Murzin
2026-07-30 10:59 ` Mark Rutland
2026-07-30 12:04 ` Vladimir Murzin
2026-07-28 12:38 ` [RFC PATCH 07/13] arm64: percpu: Implement preemptible read/write ops Mark Rutland
2026-07-28 21:47 ` David Laight
2026-08-04 15:00 ` Mark Rutland
2026-07-28 22:05 ` David Laight
2026-08-04 15:05 ` Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 08/13] arm64: percpu: Implement preemptible void RMW ops Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 09/13] arm64: percpu: Implement preemptible return " Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 10/13] arm64: percpu: Implement preemptible XCHG ops Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 11/13] arm64: percpu: Implement preemptible CMPXCHG ops Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 12/13] arm64: percpu: Implement preemptible CMPXCHG128 ops Mark Rutland
2026-07-28 12:38 ` [RFC PATCH 13/13] arm64: percpu: Remove _pcp_protect*() wrappers Mark Rutland
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