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Wed, 04 Mar 2026 14:52:09 -0700 Message-ID: <96e93ca0-ea10-4071-99ca-98f7219833d7@w6rz.net> Date: Wed, 4 Mar 2026 13:52:08 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: spi: Regression with v7.0-rc1 on VisionFive 2 To: Miquel Raynal , Conor Dooley Cc: Mark Brown , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, wsa+renesas@sang-engineering.com References: <20260228-ragweed-theater-b02967937353@spud> <20260228-defuse-extenuate-cf2a90ae66ea@spud> <87tsuvh6iw.fsf@bootlin.com> Content-Language: en-US From: Ron Economos In-Reply-To: <87tsuvh6iw.fsf@bootlin.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - box5620.bluehost.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - w6rz.net X-BWhitelist: no X-Source-IP: 73.162.206.103 X-Source-L: No X-Exim-ID: 1vxu8X-00000001U4z-1Nyl X-Source: X-Source-Args: X-Source-Dir: X-Source-Sender: c-73-162-206-103.hsd1.ca.comcast.net ([10.0.1.180]) [73.162.206.103]:49388 X-Source-Auth: re@w6rz.net X-Email-Count: 3 X-Org: HG=bhshared;ORG=bluehost; X-Source-Cap: d3NpeHJ6bmU7d3NpeHJ6bmU7Ym94NTYyMC5ibHVlaG9zdC5jb20= X-Local-Domain: yes X-CMAE-Envelope: MS4xfCxgz9OUNyH4ybLqoXl2XLfLnsEwg3/i/GC2EjJyW9+F751BCG3oEA6fWp2PRLkPN79Oon0lvNEnskKhMRhYRNW/mla4y7rS54SrOpasqkrzWavOzJal nP/vj4P0J6fQnYM4J+0kEriupCvrgaZbHpqy6N/54SdA/tLFAhm9pKkL1hbTpSQX2HBfUgJwzBENWmKE76wWtszLv1nY+VZunc4= On 3/4/26 09:02, Miquel Raynal wrote: > On 28/02/2026 at 15:39:01 GMT, Conor Dooley wrote: > >> On Sat, Feb 28, 2026 at 02:23:00PM +0000, Conor Dooley wrote: >>> On Sat, Feb 28, 2026 at 02:06:17PM +0000, Mark Brown wrote: >>>> On Sat, Feb 28, 2026 at 05:54:06AM -0800, Ron Economos wrote: >>>> >>>>> I'm getting an SPI failure with Linux v7.0-rc1 on the VisionFive 2 RISC-V board. >>>>> Feb 28 00:29:33 visionfive kernel: cadence-qspi 13010000.spi: QSPI is still busy after 500ms timeout. >>>>> Feb 28 00:29:33 visionfive kernel: cadence-qspi 13010000.spi: detected FIFO depth (1) different from config (256) >>>>> Feb 28 00:29:33 visionfive kernel: cadence-qspi 13010000.spi: QSPI is still busy after 500ms timeout. >>>>> Feb 28 00:29:33 visionfive kernel: cadence-qspi 13010000.spi: QSPI is still busy after 500ms timeout. >>>>> Feb 28 00:29:33 visionfive kernel: spi-nor spi1.0: operation failed with -110 >>>>> Feb 28 00:29:33 visionfive kernel: spi-nor spi1.0: probe with driver spi-nor failed with error -110 >>>> FWIW confirmed on my system: >>>> >>>> https://lava.sirena.org.uk/scheduler/job/2504026#L715 >>>> >>>> (which I didn't notice as that was just buildroot and not running >>>> kselftest-dt...). >>> This probably constitutes random speculation, but I am curious if >>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi >>> index 6e56e9d20bb06..390fa87edbaf8 100644 >>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi >>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi >>> @@ -873,9 +873,9 @@ qspi: spi@13010000 { >>> <0x0 0x21000000 0x0 0x400000>; >>> interrupts = <25>; >>> clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, >>> - <&syscrg JH7110_SYSCLK_QSPI_AHB>, >>> - <&syscrg JH7110_SYSCLK_QSPI_APB>; >>> - clock-names = "ref", "ahb", "apb"; >>> + <&syscrg JH7110_SYSCLK_QSPI_APB>, >>> + <&syscrg JH7110_SYSCLK_QSPI_AHB>; >>> + clock-names = "ref", "apb", "ahb"; >>> resets = <&syscrg JH7110_SYSRST_QSPI_APB>, >>> <&syscrg JH7110_SYSRST_QSPI_AHB>, >>> <&syscrg JH7110_SYSRST_QSPI_REF>; >>> has any impact. Going from jh7110 specific code to bulk apis is an >>> ordering change, right? >> According to Ron, it had no impact. > The other change that could be "it" is the change of order between reset > handling and clock. That would be quite messy if that was the error but > I cannot find another explanation. Ron, can you please try to revert > this patch locally and then move the clk_prepare_enable() of the APB and > AHB clocks earlier, right after the ref clock is also enabled? If the > platform fails to boot, there is maybe a weird internal relationship > with the resets. > > Otherwise can you compare the clk_get_rate() on all three clocks in both > cases? > > Thank you, > Miquèl I'm happy to help you debug this, but you have to send me a patch to the reverted file. I have no idea where the ref clock is enabled.