From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33CB34503B; Thu, 17 Jul 2025 09:21:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752744067; cv=none; b=Wx6jvuNIMw5GFm8Ju082+1auWR3jX7GCBmIN6ZxcQ5keDbinhSMvFy5X7UDDXNCHPD4XSuYI5UQHd9jsApeMyFM4LBF9Pm83vaRlwUZDCgEcLOn2zsYwE5AWVFznc0OEp9GcaYKje31+Kl1LHL4nM3tFS8uzIqhpijlHUX3M3CU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752744067; c=relaxed/simple; bh=nU19RtklzUHY7WY64Ssw7G0Wx4k8Zq+35hz9TBSimKw=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=SbHfX7trULilgGCJXiEl0GYuBhhADVT8nWGindfXpTpDym0glCJwsBnlnjPcTf7ACGvJ7+xfYQSktIA9l9k8MOqwxnp+hFOk0Oyz9b0ZOXNH6yM+rTrNTJ5MbkGMnHBjuU6LFK8WV7b+sXZV59ePnWYhGdFU0OUAczuaYlGk46U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ghiti.fr; spf=pass smtp.mailfrom=ghiti.fr; arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ghiti.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ghiti.fr Received: by mail.gandi.net (Postfix) with ESMTPSA id C455543123; Thu, 17 Jul 2025 09:20:58 +0000 (UTC) Message-ID: <96fad5ac-3ddd-44eb-b82d-03d2ddfb978c@ghiti.fr> Date: Thu, 17 Jul 2025 11:20:57 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 5/7] riscv: hwprobe: Document MIPS xmipsexectl vendor extension To: aleksa.paunovic@htecgroup.com, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jonathan Corbet Cc: Palmer Dabbelt , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org References: <20250625-p8700-pause-v4-0-6c7dd7f85756@htecgroup.com> <20250625-p8700-pause-v4-5-6c7dd7f85756@htecgroup.com> Content-Language: en-US From: Alexandre Ghiti In-Reply-To: <20250625-p8700-pause-v4-5-6c7dd7f85756@htecgroup.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdeitddvudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhepkfffgggfuffvvehfhfgjtgfgsehtjeertddtvdejnecuhfhrohhmpeetlhgvgigrnhgurhgvucfihhhithhiuceorghlvgigsehghhhithhirdhfrheqnecuggftrfgrthhtvghrnheptdfhleefjeegheevgeeljeellefgvefhkeeiffekueejteefvdevhfelvdeggeeinecukfhppedukeehrddvudefrdduheegrdduhedunecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepudekhedrvddufedrudehgedrudehuddphhgvlhhopegluddtrddugedrtddrudefngdpmhgrihhlfhhrohhmpegrlhgvgiesghhhihhtihdrfhhrpdhnsggprhgtphhtthhopedugedprhgtphhtthhopegrlhgvkhhsrgdrphgruhhnohhvihgtsehhthgvtghgrhhouhhprdgtohhmpdhrtghpthhtoheprhhosghhsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehkrhiikhdoughtsehkvghrnhgvlhdrohhrghdprhgtphhtthhopegtohhnohhrodgutheskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepphgruhhlrdifrghlmhhslhgvhiesshhifhhivhgvrdgtohhmpdhrtghpthhtohepphgrlhhmvghrsegurggssggvl hhtrdgtohhmpdhrtghpthhtoheprghouhesvggvtghsrdgsvghrkhgvlhgvhidrvgguuhdprhgtphhtthhopegtohhrsggvtheslhifnhdrnhgvth X-GND-Sasl: alex@ghiti.fr On 6/25/25 16:21, Aleksa Paunovic via B4 Relay wrote: > From: Aleksa Paunovic > > Document support for MIPS vendor extensions using the key > "RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0" and xmipsexectl vendor extension > using the key "RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL". > > Signed-off-by: Aleksa Paunovic > --- > Documentation/arch/riscv/hwprobe.rst | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > index 2aa9be272d5de1c15559a978a956bc36c34de81c..2f449c9b15bdd6b9813c9a968deca1a4c4ff9b14 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -327,6 +327,15 @@ The following keys are defined: > * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are > not supported at all and will generate a misaligned address fault. > > +* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0`: A bitmask containing the > + mips vendor extensions that are compatible with the > + :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. > + > + * MIPS > + > + * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl vendor > + extension is supported in the MIPS ISA extensions spec. > + > * :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the > thead vendor extensions that are compatible with the > :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. > FWIW, just a note that in the documentation you mentioned in patch 1, xmipsexectl extension also provides 2 barrier instructions that are not implemented in this patchset. Anyway: Reviewed-by: Alexandre Ghiti Thanks, Alex