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Mon, 06 May 2024 11:04:27 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 446B4OHa019309 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 6 May 2024 11:04:24 GMT Received: from [10.217.219.66] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 6 May 2024 04:04:19 -0700 Message-ID: <972807ff-5db7-77a0-da90-6ecc1e7c1ecb@quicinc.com> Date: Mon, 6 May 2024 16:34:15 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v1 2/2] arm64: dts: qcom: sa8775p: Set max link speed to gen4 for ep pcie Content-Language: en-US To: Dmitry Baryshkov CC: , , , , , , , , , , , , Rob Herring , Krzysztof Kozlowski , , , References: <1714494711-10322-1-git-send-email-quic_msarkar@quicinc.com> <1714494711-10322-3-git-send-email-quic_msarkar@quicinc.com> From: Mrinmay Sarkar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: WAcxryBzBVRpTLZmaEe2a0lLyIRZFnrh X-Proofpoint-GUID: WAcxryBzBVRpTLZmaEe2a0lLyIRZFnrh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-06_07,2024-05-03_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 mlxscore=0 adultscore=0 malwarescore=0 priorityscore=1501 mlxlogscore=999 impostorscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2405060076 On 4/30/2024 11:20 PM, Dmitry Baryshkov wrote: > On Tue, 30 Apr 2024 at 19:33, Mrinmay Sarkar wrote: >> Adding this change to set max link speed to gen4 as sa8775p supports >> gen4 so that pcie link can be enumerated as gen4. > Previous patches mentioned stability issues. Were they solved? Hi Dmitry, Thanks for review. Actually earlier gen4 related equalization setting was missing in driver. That's why gen4 was not stable and it was coming to gen3. With this below driver change gen4 is stable now https://lore.kernel.org/all/20240501163610.8900-1-quic_schintav@quicinc.com/ >> Signed-off-by: Mrinmay Sarkar >> --- >> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> index 0c52180..aad2cd7 100644 >> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> @@ -3730,7 +3730,7 @@ >> power-domains = <&gcc PCIE_0_GDSC>; >> phys = <&pcie0_phy>; >> phy-names = "pciephy"; >> - max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ >> + max-link-speed = <4>; >> num-lanes = <2>; >> >> status = "disabled"; >> @@ -3888,7 +3888,7 @@ >> power-domains = <&gcc PCIE_1_GDSC>; >> phys = <&pcie1_phy>; >> phy-names = "pciephy"; >> - max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ > I think you've just sent a patchset which adds this node. Is there any > reason for setting the max-link-speed to 3 just to change it to 4 > immediately? Earlier we were not sure about the root cause of the issue so limited the speed to gen3. Now as we have the solution for this issue so moving to gen4. > Thanks, > Mrinmay >> + max-link-speed = <4>; >> num-lanes = <4>; >> >> status = "disabled"; >> -- >> 2.7.4 >> >> > > -- > With best wishes > > Dmitry