Re: [PATCH v5 1/2] arm64: tegra: add ACONNECT, ADMA and AGIC nodes

[Jon Hunter <jonathanh@nvidia.com>]

On 13/06/2019 15:43, Sameer Pujar wrote:
> 
> On 6/13/2019 7:39 PM, Jon Hunter wrote:
>> On 13/06/2019 11:41, Sameer Pujar wrote:
>>> Add DT nodes for following devices on Tegra186 and Tegra194
>>>   * ACONNECT
>>>   * ADMA
>>>   * AGIC
>>>
>>> Signed-off-by: Sameer Pujar <spujar@nvidia.com>
>>> ---
>>>   changes from previous revision
>>>    * fixed size value for ranges property in aconnect
>>>
>>>   arch/arm64/boot/dts/nvidia/tegra186.dtsi | 67
>>> ++++++++++++++++++++++++++++++++
>>>   arch/arm64/boot/dts/nvidia/tegra194.dtsi | 67
>>> ++++++++++++++++++++++++++++++++
>>>   2 files changed, 134 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> index 426ac0b..5e9fe7e 100644
>>> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
>>> @@ -1295,4 +1295,71 @@
>>>                   (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>>>           interrupt-parent = <&gic>;
>>>       };
>>> +
>>> +    aconnect {
>>> +        compatible = "nvidia,tegra210-aconnect";
>>> +        clocks = <&bpmp TEGRA186_CLK_APE>,
>>> +             <&bpmp TEGRA186_CLK_APB2APE>;
>>> +        clock-names = "ape", "apb2ape";
>>> +        power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
>>> +        #address-cells = <1>;
>>> +        #size-cells = <1>;
>>> +        ranges = <0x02900000 0x0 0x02900000 0x200000>;
>>> +        status = "disabled";
>>> +
>>> +        dma-controller@2930000 {
>>> +            compatible = "nvidia,tegra186-adma";
>>> +            reg = <0x02930000 0x50000>;
>> Sorry but I have been double checking these register addresses and I
>> wonder if this should be a length of 0x10000. The 0x50000 includes all
>> the ranges where the registers are paged, so I don't think that this is
>> correct including these.
> Is it because we don't have virtualization support yet?

Yes those are for virtulisation, but I don't believe we need them here.

> and isn't the range 0x10000 covers only global register space, don't we
> want to include page1 ADMA channel registers. In that case it would be
> 0x20000.

Yes, 0x20000 is correct indeed

Cheers
Jon

-- 
nvpublic