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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-89077284f23sm24910446d6.57.2026.01.06.18.47.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 06 Jan 2026 18:47:22 -0800 (PST) Message-ID: <9730440b-b4ef-4b9a-ac77-37945c5b4f5c@oss.qualcomm.com> Date: Wed, 7 Jan 2026 10:47:14 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] arm64: dts: qcom: talos: Add CCI definitions To: Dmitry Baryshkov Cc: Loic Poulain , Robert Foss , Andi Shyti , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Todor Tomov , Bryan O'Donoghue , Vladimir Zapolskiy , linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org References: <20260106-sm6150_evk-v2-0-bb112cb83d74@oss.qualcomm.com> <20260106-sm6150_evk-v2-2-bb112cb83d74@oss.qualcomm.com> Content-Language: en-US From: Wenmeng Liu In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA3MDAyMSBTYWx0ZWRfXxMGGUCeT3Jsx er17LjY80pL8CSoFHcKzlgRZ4hPm4uqt3KUFW7sOyRqgqbkDVukHen995LYQ82JBsEuRjOy/QUB wfB6w833aX3jTWkIhPDVata9U+KTr4LQJfTByUbj2R19rLmyWp60lqSWLe5X9cD0sEBrBd3rkTf rlijxepWULroFRsW6c4CZIO/ZZdzTMQWvrUyRDz+Bjng9wBGbT+2dpAh8JAkbEvfFPg5Dk90MjZ 817hcsB245Gm5cYL06G0KB/hbIa+ImB9HyATTfEPlzaqAhk9g1kAD5cptipl4JuGfNdH3eDBacY mKDkCNteA+HOFBh4ZKc6EFMIKaCMBaIqXT77fKSV/MgyajoavkxBIUYw0fYrDNYF7Utp6RwMDeZ YFTqAcQT3HBtRuUJsF5m1I9kSlu0PYB1l6Lj4tjcCc+URrZ7axgwpBx8rqTuF3PoGyh4Y1ylcij wkSylTUhLnFn4pEA8Dw== X-Authority-Analysis: v=2.4 cv=VI7QXtPX c=1 sm=1 tr=0 ts=695dc93d cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=eyU4tusHGcKmyRKv_OMA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 X-Proofpoint-GUID: ZFIAkkudEkXpX9dqwbPhjClWYNlZwW3N X-Proofpoint-ORIG-GUID: ZFIAkkudEkXpX9dqwbPhjClWYNlZwW3N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-06_03,2026-01-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 suspectscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 adultscore=0 bulkscore=0 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601070021 On 1/7/2026 2:27 AM, Dmitry Baryshkov wrote: > On Tue, Jan 06, 2026 at 05:39:54PM +0800, Wenmeng Liu wrote: >> Qualcomm Talos SoC contains single controller, >> containing 2 I2C hosts. >> >> Signed-off-by: Wenmeng Liu >> --- >> arch/arm64/boot/dts/qcom/talos.dtsi | 72 +++++++++++++++++++++++++++++++++++++ >> 1 file changed, 72 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi >> index e1dfaff9b6bf8641b19a685e74d60ad4e1e99d41..461a39968d928260828993ff3549aa15fd1870df 100644 >> --- a/arch/arm64/boot/dts/qcom/talos.dtsi >> +++ b/arch/arm64/boot/dts/qcom/talos.dtsi >> @@ -1549,6 +1549,42 @@ tlmm: pinctrl@3100000 { >> #interrupt-cells = <2>; >> wakeup-parent = <&pdc>; >> >> + cci_default: cci0-default-state { >> + cci_i2c0_default: cci-i2c0-default-pins { > > These need to be split, having just one host per state. ACK.> >> + /* SDA, SCL */ >> + pins = "gpio32", "gpio33"; >> + function = "cci_i2c"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + cci_i2c1_default: cci-i2c1-default-pins { >> + /* SDA, SCL */ >> + pins = "gpio34", "gpio35"; >> + function = "cci_i2c"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + }; >> + >> + cci_sleep: cci-sleep-state { >> + cci_i2c0_sleep: cci-i2c0-sleep-state { > > The same ACK.> >> + /* SDA, SCL */ >> + pins = "gpio32", "gpio33"; >> + function = "cci_i2c"; >> + drive-strength = <2>; >> + bias-pull-down; >> + }; >> + >> + cci_i2c1_sleep: cci-i2c1-sleep-state { >> + /* SDA, SCL */ >> + pins = "gpio34", "gpio35"; >> + function = "cci_i2c"; >> + drive-strength = <2>; >> + bias-pull-down; >> + }; >> + }; >> + >> qup_i2c1_data_clk: qup-i2c1-data-clk-state { >> pins = "gpio4", "gpio5"; >> function = "qup0"; >> @@ -3785,6 +3821,42 @@ videocc: clock-controller@ab00000 { >> #power-domain-cells = <1>; >> }; >> >> + cci: cci@ac4a000 { >> + compatible = "qcom,sm6150-cci", "qcom,msm8996-cci"; >> + >> + reg = <0x0 0x0ac4a000 0x0 0x4000>; > > Extra double space. ACK.> >> + interrupts = ; >> + power-domains = <&camcc TITAN_TOP_GDSC>; >> + clocks = <&camcc CAM_CC_SOC_AHB_CLK>, >> + <&camcc CAM_CC_CPAS_AHB_CLK>, >> + <&camcc CAM_CC_CCI_CLK>; >> + clock-names = "soc_ahb", >> + "cpas_ahb", >> + "cci"; >> + pinctrl-0 = <&cci_default>; >> + pinctrl-1 = <&cci_sleep>; >> + pinctrl-names = "default", "sleep"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + >> + cci_i2c0: i2c-bus@0 { >> + reg = <0>; >> + clock-frequency = <1000000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + >> + cci_i2c1: i2c-bus@1 { >> + reg = <1>; >> + clock-frequency = <1000000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + }; >> + >> camss: isp@acb3000 { >> compatible = "qcom,sm6150-camss"; >> >> >> -- >> 2.34.1 >> > Will fix in next version. Thanks, Wenmeng