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[146.241.106.155]) by smtp.gmail.com with ESMTPSA id e5-20020a05600c4e4500b0040772934b12sm3628902wmq.7.2023.11.02.09.24.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Nov 2023 09:24:16 -0700 (PDT) Message-ID: <97732cc0a75c0be3f2354075085e7fa6d78e82bb.camel@redhat.com> Subject: Re: [PATCH net 6/7] net: hns3: fix VF reset fail issue From: Paolo Abeni To: Jijie Shao , yisen.zhuang@huawei.com, salil.mehta@huawei.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org Cc: shenjian15@huawei.com, wangjie125@huawei.com, liuyonglong@huawei.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Date: Thu, 02 Nov 2023 17:24:14 +0100 In-Reply-To: References: <20231028025917.314305-1-shaojijie@huawei.com> <20231028025917.314305-7-shaojijie@huawei.com> <9bc9514044063bc57155fb786f970ca1d69758b4.camel@redhat.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.4 (3.46.4-1.fc37) MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2023-11-02 at 20:16 +0800, Jijie Shao wrote: > on 2023/11/2 18:45, Paolo Abeni wrote: > > On Sat, 2023-10-28 at 10:59 +0800, Jijie Shao wrote: > > > =20 > > > -static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 = regclr) > > > +static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 = regclr, > > > + bool need_dalay) > > > { > > > +#define HCLGEVF_RESET_DELAY 5 > > > + > > > + if (need_dalay) > > > + mdelay(HCLGEVF_RESET_DELAY); > > 5ms delay in an interrupt handler is quite a lot. What about scheduling > > a timer from the IH to clear the register when such delay is needed? > >=20 > > Thanks! > >=20 > > Paolo >=20 > Using timer in this case will complicate the code and make maintenance di= fficult. Why?=20 Would something alike the following be ok? (plus reset_timer initialization at vf creation and cleanup at vf removal time): --- diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/dr= ivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c index a4d68fb216fb..626bc67065fc 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c @@ -1974,6 +1974,14 @@ static enum hclgevf_evt_cause hclgevf_check_evt_caus= e(struct hclgevf_dev *hdev, return HCLGEVF_VECTOR0_EVENT_OTHER; } =20 +static void hclgevf_reset_timer(struct timer_list *t) +{ + struct hclgevf_dev *hdev =3D from_timer(hclgevf_dev, t, reset_timer); + + hclgevf_clear_event_cause(hdev, HCLGEVF_VECTOR0_EVENT_RST); + hclgevf_reset_task_schedule(hdev); +} + static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data) { enum hclgevf_evt_cause event_cause; @@ -1982,13 +1990,13 @@ static irqreturn_t hclgevf_misc_irq_handle(int irq,= void *data) =20 hclgevf_enable_vector(&hdev->misc_vector, false); event_cause =3D hclgevf_check_evt_cause(hdev, &clearval); + if (event_cause =3D=3D HCLGEVF_VECTOR0_EVENT_RST) + mod_timer(hdev->reset_timer, jiffies + msecs_to_jiffies(5)); + if (event_cause !=3D HCLGEVF_VECTOR0_EVENT_OTHER) hclgevf_clear_event_cause(hdev, clearval); =20 switch (event_cause) { - case HCLGEVF_VECTOR0_EVENT_RST: - hclgevf_reset_task_schedule(hdev); - break; case HCLGEVF_VECTOR0_EVENT_MBX: hclgevf_mbx_handler(hdev); break; --- > We consider reducing the delay time by polling. For example, > the code cycles every 50 us to check whether the write register takes eff= ect. > If yes, the function returns immediately. or the code cycles until 5 ms. >=20 > Is this method appropriate? IMHO such solution will not remove the problem. How frequent is expected to be the irq generating such delay? Thanks Paolo