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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b8f708e25dasm146980766b.4.2026.02.12.03.46.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Feb 2026 03:46:23 -0800 (PST) Message-ID: <97af21d5-7457-4dc1-bd47-2e34e6df094e@oss.qualcomm.com> Date: Thu, 12 Feb 2026 12:46:21 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add second TC9563 PCIe switch node for PCIe1 To: Sushrut Shree Trivedi , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov References: <20260212-industrial-mezzanine-pcie-v3-0-1e152937a76a@oss.qualcomm.com> <20260212-industrial-mezzanine-pcie-v3-2-1e152937a76a@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260212-industrial-mezzanine-pcie-v3-2-1e152937a76a@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=BbPVE7t2 c=1 sm=1 tr=0 ts=698dbd91 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=Mpw57Om8IfrbqaoTuvik:22 a=GgsMoib0sEa3-_RKJdDe:22 a=EUspDBNiAAAA:8 a=0eh1lDOh_YGwDaDwIBMA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-GUID: eTIGlarggClINsplHlMFrT0xAzWXdo0u X-Proofpoint-ORIG-GUID: eTIGlarggClINsplHlMFrT0xAzWXdo0u X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjEyMDA4OCBTYWx0ZWRfX+ih2WpOutsFn ErBGdXKnzxMJVSt0eBiiOrt04FnrcNdHr/89l31+sF35o/iBUKtDtzf8aQPniskaBXeeChlH+Q7 cnw474pjOuRXKTahfqg2wHxtUsutlysk9IsYQ0kUvIHA2APD87pnCri4TjmQsg2Me0YTitA7MCa IH+VFQuxFXrTFSwyWmPHD1snf7cqcVR1x1OCQzfPC4NfgPqSOxiWiWTt9BZ2Pv5OQbCkCBClZ52 VtlKnadoq1ZFVWkcjrZ5Y9sBKV2D4MOKqSbStwOGo6sWc8iCjF8s+0sak48GpGbbZ8R0j0x5u8M Fl+/1xNFxx113h5U8yNlgQE0praGIxHtKAb2HtH1KtO2+IuXPwfQHIqhR3ga/xLrkmbRijHs/SP yQVfaI8doXrz1kC5LvPxi6hmzN04DjsSCw/mfW5pnDtPT22b+7xMiX7TvajB5hnG+PQ8LyBsLn8 TXIZLbuwfebO7rJ8qCA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-12_03,2026-02-11_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 phishscore=0 spamscore=0 impostorscore=0 malwarescore=0 suspectscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2602120088 On 2/12/26 11:44 AM, Sushrut Shree Trivedi wrote: > Add a node for the second TC9563 PCIe switch on PCIe1, which is connected > in cascade to the first TC9563 switch via the former's downstream port. > > Two embedded Ethernet devices are present on one of the downstream > ports of this second switch as well. All the ports present in the > node represent the downstream ports and embedded endpoints. > > The second TC9563 is powered up via the same LDO regulators as the first > one, and these can be controlled via two GPIOs, which are already present > as fixed regulators. This TC9563 can also be configured through I2C. > > Signed-off-by: Sushrut Shree Trivedi > --- > +&pcie1 { > + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, > + <0x100 &apps_smmu 0x1c81 0x1>, > + <0x208 &apps_smmu 0x1c84 0x1>, > + <0x210 &apps_smmu 0x1c85 0x1>, > + <0x218 &apps_smmu 0x1c86 0x1>, > + <0x300 &apps_smmu 0x1c87 0x1>, > + <0x408 &apps_smmu 0x1c90 0x1>, > + <0x410 &apps_smmu 0x1c91 0x1>, > + <0x418 &apps_smmu 0x1c92 0x1>, > + <0x500 &apps_smmu 0x1c93 0x1>, > + <0x600 &apps_smmu 0x1c94 0x1>, > + <0x700 &apps_smmu 0x1c95 0x1>, > + <0x701 &apps_smmu 0x1c96 0x1>, > + <0x800 &apps_smmu 0x1c97 0x1>, > + <0x900 &apps_smmu 0x1c98 0x1>, > + <0x901 &apps_smmu 0x1c99 0x1>; This map is not just an extension of the existing one - is that intentional? Konrad