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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 12/09/2024 13:44, Vladimir Zapolskiy wrote: >> csiphy0 >> >> vdda-phy-supply = <&vreg_l2c_0p9>; >> vdda-pll-supply = <&vreg_l1c_1p2>; >> >> This is also the case for csiphy 1/2/4 >> >> So, I _don't_ believe this is work we need to do, since its the same >> regulator for each PHY. > > This is board specific, and even if the separation is not needed on the > boards > you have just checked, still it may be needed on some boards, which are > not yet > checked/not yet known. There is a Power Grid Analysis document which specifies these rails @ the SoC level and assumes you've used the Qcom PMIC to power, moreover the PGA re-uses the same regulator over and over again. You _could_ provide that power from your own PMIC which provides the same voltage range as the Qcom PMIC you haven't used. Even if you did provide that from your own PMIC you'd have to provide _separate_ rails for the various CSIPHYs before it would be required to have a per PHY rail requirement on this SoC. Are people really powering these SoCs with their own PMICs ? No probably not. Should we add the support for it anyway ? Maybe. So to reiterate: 1. csiphyX-vdda-phy-supply csiphyX-vdda-pll-supply In the dts and yaml => The names should be generic from the perspective of the driver 2. camss.c::csiphy_res_sm8550 [0].regulators = { "csiphy0-vdda-phy-supply", "csiphy0-vdda-pll-supply" } ... [N].regulators = { "csiphyN-vdda-phy-supply", "csiphyN-vdda-pll-supply" } => The regulators for the PHY should be defined in the PHY resources description 3. Required not optional in the yaml => You can't use the PHY without its regulators --- bod