From mboxrd@z Thu Jan 1 00:00:00 1970 Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751523AbeAGBoz (ORCPT + 1 other); Sat, 6 Jan 2018 20:44:55 -0500 Received: from mail-cys01nam02on0086.outbound.protection.outlook.com ([104.47.37.86]:56554 "EHLO NAM02-CY1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751131AbeAGBox (ORCPT ); Sat, 6 Jan 2018 20:44:53 -0500 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Thomas.Lendacky@amd.com; Subject: Re: [PATCH v5 02/12] x86/retpoline: Add initial retpoline support To: "Woodhouse, David" , Andrew Cooper , Andi Kleen Cc: Paul Turner , LKML , Linus Torvalds , Greg Kroah-Hartman , Tim Chen , Dave Hansen , tglx@linutronix.de, Kees Cook , Rik van Riel , Peter Zijlstra , Andy Lutomirski , Jiri Kosina , gnomes@lxorguk.ukuu.org.uk References: <1515239374-23361-1-git-send-email-dwmw@amazon.co.uk> <1515239374-23361-3-git-send-email-dwmw@amazon.co.uk> <0c150bb9-f5eb-2bf2-1f64-84c1b315868b@citrix.com> <1515273680.29312.272.camel@amazon.co.uk> From: Tom Lendacky Message-ID: <98026f36-a283-f054-a8df-7be1ba59803e@amd.com> Date: Sat, 6 Jan 2018 19:44:38 -0600 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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>>>        setup_force_cpu_bug(X86_BUG_SPECTRE_V2); >>> +#ifdef CONFIG_RETPOLINE >>> +     setup_force_cpu_cap(X86_FEATURE_RETPOLINE); >>> +     if (c->x86_vendor == X86_VENDOR_AMD) >>> +             setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); >> >> This isn't safe.  It needs to be dependant on finding that LFENCEs are >> actually dispatch serialising. >> >> In particular, when virtualised, you'll most likely be saddled with the >> hypervisors choice of setting, in which case you need to use retpoline >> as a fallback. > > Thanks. I was about to rebase on top of tip/x86/pti which has Tom's > patches to make lfence serialising — which seem to say that if the MSR > isn't available, it *will* be serialising. > > I think I'll just refrain from setting X86_FEATURE_RETPOLINE_AMD for > now, and let Tom turn that on in his own time. I can do that. I'll move it to arch/x86/kernel/cpu/amd.c to just after the line that sets the MSR bit making lfence serializing. I'll submit that once your patches are pulled in (or at least the feature bits). Thanks, Tom >