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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e7e90a07sm987503366b.6.2025.07.15.04.47.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Jul 2025 04:47:40 -0700 (PDT) Message-ID: <98088092-1987-41cc-ab70-c9a5d3fdbb41@oss.qualcomm.com> Date: Tue, 15 Jul 2025 13:47:37 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/4] arm64: dts: qcom: sa8775p: remove aux clock from pcie phy To: Ziyue Zhang , Johan Hovold Cc: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com References: <20250625090048.624399-1-quic_ziyuzhan@quicinc.com> <20250625090048.624399-4-quic_ziyuzhan@quicinc.com> <25ddb70a-7442-4d63-9eff-d4c3ac509bbb@oss.qualcomm.com> <4f963fcc-2b92-4a01-93a4-f0ae942c1b6f@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <4f963fcc-2b92-4a01-93a4-f0ae942c1b6f@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=dKimmPZb c=1 sm=1 tr=0 ts=68763fdf cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=dJGf4bKP5mfmDP1ZOs4A:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-GUID: lYuzbQF6LJHiBOiG-56UmuEjdd5Yw_s6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE1MDEwNyBTYWx0ZWRfXx8PbcjAFDpRm K0KWe4WXU6WmSOopHGsQVXrsMto/+KTfeO1coY0YEPefsqvjArTC12CkKjuB+bnL6pA3WmKAhuM lt0/U3ENmw4TruXxm4ZBF9erGHVVpH9ubj9E3TiOiWgEbsTWcxOxjhWCnllwTgAofVizh3Vrzz9 uP4tbimgfRc1cY5hkl4X+05I5CJlwsKS9U6fEByea7iCswzkfPfwj9VbLcThT5LnisecEeV5NKW 23w+yv89/R0ql3HwWZZuKHfuIYqN8Rf3rZKGk61vyQHgeuUfFn67+7malVNBITIC9ozj/sJj9N3 HYEpdzg8UbtWSYGWsrv/7LInLpqDGNsC8rqAqBSSBUxka3ZEPTp5CTpaI6/3EkR2pDY9CT08fZ0 bbdMpZbSWOcTbkXWZw1znwTKMMh8SdORI7KZdjLQb99AYlXmbcreFaqDoNNrT39/vNOGn3Kg X-Proofpoint-ORIG-GUID: lYuzbQF6LJHiBOiG-56UmuEjdd5Yw_s6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-15_01,2025-07-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 spamscore=0 adultscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507150107 On 7/10/25 12:24 PM, Ziyue Zhang wrote: > > On 7/10/2025 5:43 PM, Johan Hovold wrote: >> On Fri, Jun 27, 2025 at 04:50:57PM +0200, Konrad Dybcio wrote: >>> On 6/25/25 11:00 AM, Ziyue Zhang wrote: >>>> gcc_aux_clk is used in PCIe RC and it is not required in pcie phy, in >>>> pcie phy it should be gcc_phy_aux_clk, so remove gcc_aux_clk and >>>> replace it with gcc_phy_aux_clk. >>> GCC_PCIE_n_PHY_AUX_CLK is a downstream of the PHY's output.. >>> are you sure the PHY should be **consuming** it too? >> Could we get a reply here, please? >> >> A bunch of Qualcomm SoCs in mainline do exactly this currently even >> though it may not be correct (and some downstream dts do not use these >> clocks). >> >> Johan > > Hi Johan > > After reviewing the downstream platforms, it seems that GCC_PCIE_n_PHY_AUX_CLK > is generally needed. Would you mind letting us know if there are any platforms > where this clock is not required? Do you base this on "downstream has it", or did you check with the relevant folks internally? I'm still unconvinced by the clock looping back to the PHY. Konrad