From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753833AbdKMQcJ (ORCPT ); Mon, 13 Nov 2017 11:32:09 -0500 Received: from mail-lf0-f42.google.com ([209.85.215.42]:53757 "EHLO mail-lf0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753762AbdKMQcH (ORCPT ); Mon, 13 Nov 2017 11:32:07 -0500 X-Google-Smtp-Source: AGs4zMZETFjTfqlWYOeJOwv5WcaTWBKDwIR/vkRcBL281CzhY4K68icRYmW50Ab2UF0uwE+syaS+EA== Subject: Re: [patch v2 3/8] KVM: x86: add Intel processor trace virtualization mode To: Luwei Kang , kvm@vger.kernel.org Cc: rkrcmar@redhat.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-kernel@vger.kernel.org, Chao Peng References: <1509401117-15521-1-git-send-email-luwei.kang@intel.com> <1509401117-15521-4-git-send-email-luwei.kang@intel.com> From: Paolo Bonzini Message-ID: <9838721f-ed64-cec8-f3dc-895c0bb7a681@redhat.com> Date: Mon, 13 Nov 2017 17:32:00 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: <1509401117-15521-4-git-send-email-luwei.kang@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30/10/2017 23:05, Luwei Kang wrote: > + if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_PT_USE_GPA) || > + !(_vmexit_control & VM_EXIT_CLEAR_IA32_RTIT_CTL) || > + !(_vmentry_control & VM_ENTRY_LOAD_IA32_RTIT_CTL)) { > + _cpu_based_2nd_exec_control &= ~SECONDARY_EXEC_PT_USE_GPA; Also, you are not checking anywhere if the SUPPRESS_PIP controls are available. This is probably the best place. > + _vmexit_control &= ~VM_EXIT_CLEAR_IA32_RTIT_CTL; > + _vmentry_control &= ~VM_ENTRY_LOAD_IA32_RTIT_CTL; These two are not needed; disabling SECONDARY_EXEC_PT_USE_GPA is enough. The tracing mode will revert to PT_SYSTEM, which does not use the load/clear RTIT_CTL controls. Paolo > + } > +