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Wed, 21 Oct 2026 05:01:59 -0700 (PDT) Received: from [10.217.240.81] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ad80303567sm4221616a91.14.2026.10.21.05.01.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 05:01:58 -0700 (PDT) Message-ID: <984bc755-07f1-4c7e-9efe-ecc6b2ee5d5f@oss.qualcomm.com> Date: Wed, 21 Oct 2026 17:31:51 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] edac: qcom: add LCP/SRP DDR DRAM ECC support for Shikra To: Jonathan Cameron Cc: Bjorn Andersson , Konrad Dybcio , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam , Borislav Petkov , Tony Luck , Conor Dooley , Abel Vesa , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org References: <20261014-master-v1-0-aba3cfcfbac9@oss.qualcomm.com> <20261014-master-v1-3-aba3cfcfbac9@oss.qualcomm.com> <20261016182608.65bae12d@jic23-hlaptop> Content-Language: en-US From: Faiyaz Mohammed In-Reply-To: <20261016182608.65bae12d@jic23-hlaptop> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA0NyBTYWx0ZWRfXwDjfC4Qbv4JD Y2/iTVjDkzqK8botxFLVukIVU5+l5sXAXLIYbYgFopoZg336bHSbVfo60EV2dV3Y9piWyXiqDjr 0dNpezH1Y9dFtTXnKCl2GUF1SkjLvzs= X-Proofpoint-GUID: HgXN1Bn-sCkKHUyYBj-QqrlTn7r-dgYS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA0NyBTYWx0ZWRfX8v3IAebIVl0r nfXyLH7TMbA3AQfk7R+YeV6jvyCC3R2RWU6nogke/9rLBiI6aZI/xiYrLBg8o0xTb1tM34WLnaY V+D1dgcj5V9CizehqnJWq6CSzb4AFZuaOlu6TETH2ob6BFm3kHbumOn+LmR51N7p7V2D8CMfNfo AtdVjD5FDQS5whRYEiR5C+JFkUrir3cr9CyGxz5W8WKmcWJfjpUQIu98lStemYjnTUCi3nsUbny Kp5Kwn0zCJR/RIyLnHB7glhOjjmd4JBDM8nCgJWwIUD3V5ENZcY3janY3+Iaxm1jxJa4sqySUvu /wv6Gp2qz/Y6rqNh5A+pS9oiz8tg1DxgX0QvKB35o9PL88ojrj8/xt6MksV6bemNJjjNsckAHqM Rdxq/UKsphc3rp6ufk3L16DLiWngxAa7h/o/R0ymytTRqWFzT20QvfV+w1SJboSrsw3zOJOYFux QnGW0Fe/+WBrHPq2exw== X-Authority-Analysis: v=2.4 cv=R42WitRX c=1 sm=1 tr=0 ts=6ad8a9bb cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=7hEWZ4R0ReQgp7LtlT8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: HgXN1Bn-sCkKHUyYBj-QqrlTn7r-dgYS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_03,2026-10-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 spamscore=0 malwarescore=0 adultscore=0 clxscore=1015 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210047 On 16-10-2026 22:56, Jonathan Cameron wrote: > On Wed, 14 Oct 2026 21:26:18 +0530 > Faiyaz Mohammed wrote: > >> Add qcom_llcc_lcp_setup() to enable LCP/SRP interrupt routing when >> firmware has not pre-configured it, and llcc_lcp_ecc_irq_handler() to >> report per-bank correctable and uncorrectable DDR DRAM ECC errors. >> >> LCP/SRP setup is skipped when ecc_irq_configured is set (e.g. Shikra, >> where DSF firmware handles IRQ routing). A missing lcp_irq is >> non-fatal; TRP/DRP ECC reporting continues unaffected. >> >> Signed-off-by: Faiyaz Mohammed > Trivial stuff only inline. > >> --- >> drivers/edac/qcom_edac.c | 147 +++++++++++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 147 insertions(+) >> >> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c >> index f3da9385ca0d..b4f7b2493650 100644 >> --- a/drivers/edac/qcom_edac.c >> +++ b/drivers/edac/qcom_edac.c > >> /* Clear the error interrupt and counter registers */ >> static int >> qcom_llcc_clear_error_status(int err_type, struct llcc_drv_data *drv) >> @@ -334,6 +366,92 @@ static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl) >> llcc_ecc_irq_handler(0, edev_ctl); >> } >> >> +/* >> + * Handler for the optional LCP/SRP DDR DRAM ECC interrupt >> + * (ddrss_apps_interrupt[1]). The LCP/SRP registers live in each LLCC >> + * instance's address space, so iterate over all banks and read status >> + * per-instance. Broadcast-write the clear after the full loop, mirroring >> + * the TRP/DRP handler pattern. >> + */ >> +static irqreturn_t llcc_lcp_ecc_irq_handler(int irq, void *edev_ctl) >> +{ >> + struct edac_device_ctl_info *edac_dev_ctl = edev_ctl; >> + struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data; >> + const struct llcc_edac_reg_offset *reg = drv->edac_reg_offset; >> + irqreturn_t irq_rc = IRQ_NONE; >> + u32 intr_status, err_status, clr_reg; >> + int i, ret; >> + >> + /* Iterate over banks: LCP/SRP status registers are per-LLCC instance */ >> + for (i = 0; i < drv->num_banks; i++) { > for (int i = 0; > > Fine in modern kernel code and makes scope more explicit. > Done. >> + ret = regmap_read(drv->regmaps[i], reg->lcp_srp_interrupt_status, > > I'd use a local variable to hold the regmap pointer. > Done — added struct regmap *regmap = drv->regmaps[i] at the top of the loop body. >> + &intr_status); >> + if (ret) > > A read fail, without any logging seems unwise as you may have just jumped the > error. > Good point — added edac_printk(KERN_ERR) for the interrupt status read failure, consistent with the error status read path below it. >> + continue; >> + >> + intr_status &= LCP_SB_ECC_ERROR | LCP_DB_ECC_ERROR; >> + if (!intr_status) >> + continue; >> + >> + irq_rc = IRQ_HANDLED; >> + >> + ret = regmap_read(drv->regmaps[i], reg->lcp_srp_ecc_error_status1, >> + &err_status); >> + if (ret) { >> + edac_printk(KERN_ERR, EDAC_LLCC, >> + "LCP/SRP error status read failed for bank%u: %d\n", >> + i, ret); >> + continue; >> + } >> + >> + if (intr_status & LCP_DB_ECC_ERROR) { >> + u32 db_cnt = FIELD_GET(LCP_DB_ERR_COUNT_MASK, err_status); >> + >> + edac_printk(KERN_CRIT, EDAC_LLCC, >> + "LCP/SRP DDR DRAM Double-bit ECC error in bank%u: count=%u status=0x%08x\n", >> + i, db_cnt, err_status); >> + edac_device_handle_ue(edac_dev_ctl, 0, i, >> + "LCP/SRP DDR DRAM uncorrectable error"); >> + } >> + >> + if (intr_status & LCP_SB_ECC_ERROR) { >> + u32 sb_cnt = FIELD_GET(LCP_SB_ERR_COUNT_MASK, err_status); >> + >> + edac_printk(KERN_WARNING, EDAC_LLCC, >> + "LCP/SRP DDR DRAM Single-bit ECC error in bank%u: count=%u status=0x%08x\n", >> + i, sb_cnt, err_status); >> + edac_device_handle_ce(edac_dev_ctl, 0, i, >> + "LCP/SRP DDR DRAM correctable error"); >> + } >> + } >> + >> + if (irq_rc != IRQ_HANDLED) >> + return irq_rc; >> + >> + clr_reg = reg->lcp_srp_interrupt_clear ? >> + reg->lcp_srp_interrupt_clear : >> + reg->lcp_srp_interrupt_status; >> + >> + if (clr_reg) { >> + ret = regmap_write(drv->bcast_regmap, clr_reg, >> + LCP_SB_ECC_ERROR | LCP_DB_ECC_ERROR); >> + if (ret) >> + edac_printk(KERN_ERR, EDAC_LLCC, >> + "LCP/SRP interrupt clear failed: %d\n", ret); >> + } >> + >> + if (reg->lcp_srp_ecc_error_cntr_clear) { >> + ret = regmap_write(drv->bcast_regmap, >> + reg->lcp_srp_ecc_error_cntr_clear, >> + DRP_TRP_CNT_CLEAR); >> + if (ret) >> + edac_printk(KERN_ERR, EDAC_LLCC, >> + "LCP/SRP counter clear failed: %d\n", ret); >> + } >> + >> + return irq_rc; >> +} >> + >> static int qcom_llcc_edac_probe(struct platform_device *pdev) >> { >> struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data; >> @@ -372,6 +490,8 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) >> edac_op_state = EDAC_OPSTATE_INT; >> goto irq_done; >> } >> + dev_warn(dev, "failed to request LLCC ECC irq %d: %d, falling back to polling\n", >> + ecc_irq, rc); >> } >> >> /* Fall back to polling mode otherwise */ >> @@ -386,6 +506,33 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) >> return rc; >> } >> >> + /* >> + * Set up LCP/SRP DDR DRAM ECC after the EDAC device is published. >> + * Skip hardware routing setup if firmware already configured IRQ >> + * propagation (irq_configured); only request the IRQ handler. >> + * Guard on a non-zero lcp_srp_interrupt_enable offset to confirm >> + * this LLCC variant actually has an LCP/SRP block. >> + */ >> + if (llcc_driv_data->lcp_irq > 0 && >> + llcc_driv_data->edac_reg_offset->lcp_srp_interrupt_enable) { >> + if (!llcc_driv_data->ecc_irq_configured) { >> + rc = qcom_llcc_lcp_setup(llcc_driv_data, >> + llcc_driv_data->bcast_regmap); >> + if (rc) { >> + dev_warn(dev, "LCP/SRP interrupt setup failed: %d\n", rc); > >> + goto lcp_done; >> + } >> + } >> + rc = devm_request_irq(dev, llcc_driv_data->lcp_irq, >> + llcc_lcp_ecc_irq_handler, >> + 0, "llcc_lcp_ecc", edev_ctl); >> + if (rc) >> + dev_warn(dev, >> + "failed to request LCP ECC irq %d: %d, DDR DRAM ECC reporting disabled\n", >> + llcc_driv_data->lcp_irq, rc); >> + } >> +lcp_done: >> + rc = 0; >> platform_set_drvdata(pdev, edev_ctl); >> >> return rc; >> > Thanks & regards, Mohammed Faiyaz