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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: L--e6aBSFSOg7tdsP_fR9FTBbKp_2wzX X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE3MDE1NSBTYWx0ZWRfX6xx0LtrPDa5g f+lZgIy/yHPLRKJxjctS58UzIx2OkDPvQwDHvqJl6rjv4gFIqwAg3y9PTCCT8V1mi6wEBMDxqdA sHlnaFJDcYiLqyEWdDJug1aYlRuo9iXNTQRqIIO0PTYNrnDQkk5tc1YFsldJ2tHsW+fyIH4X8Fa i/hbI2KiE5l3Tg8uYZAEoUTFPvuTavPwM938nkuZwjxBdxzX0oKZJEfZJkqt3GbtzR5jdXFM1aa Qp/oBvfcwmwTDkPKd5yEVFoOoWdGAagdpo/4mIgFccsBJpp4NWeXSnFlKaH2mZXmfUQ+clToLvW rbY6HIVRE94C+/Dyd/ajtG1BwRZDfQV5hBZTJvCj3eaQabFDiGpnLRi/V1AdSSkGIWSXJAw+jKV 0oiBXafA4PyiV4OqzDxcvkgG+6wfgDHbtGMyWpfqpuzU6Q2F8uwzimcn9FcyamvjWnuiohlMHYS qo4qWkOPmuhm5HTMVKA== X-Authority-Analysis: v=2.4 cv=b4mCJNGx c=1 sm=1 tr=0 ts=69e25152 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=0AyAw_TJNaHdl9VPQ8YA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: L--e6aBSFSOg7tdsP_fR9FTBbKp_2wzX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-17_01,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 adultscore=0 bulkscore=0 phishscore=0 clxscore=1015 spamscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604170155 On 4/14/2026 7:39 PM, Konrad Dybcio wrote: > On 4/14/26 7:00 AM, Vishnu Reddy wrote: >> From: Mukesh Ojha >> >> Most Qualcomm platforms feature a proprietary hypervisor (such as Gunyah >> or QHEE), which typically handles IOMMU configuration. This includes >> mapping memory regions and device memory resources for remote processors >> by intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are >> later removed during teardown. Additionally, SHM bridge setup is required >> to enable memory protection for both remoteproc metadata and its memory >> regions. >> >> When the hypervisor is absent, the operating system must perform these >> configurations instead. >> >> Support for handling IOMMU and SHM setup in the absence of a hypervisor >> is now in place. Extend the Iris driver to enable this functionality on >> platforms where IOMMU is managed by Linux (i.e., non-Gunyah, non-QHEE). >> >> Additionally, the Iris driver must map the firmware and its required >> resources to the firmware SID, which is now specified via iommu-map in >> the device tree. >> >> Co-developed-by: Vikash Garodia >> Signed-off-by: Vikash Garodia >> Signed-off-by: Mukesh Ojha >> Signed-off-by: Vishnu Reddy >> --- > [...] > >> static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name) >> { >> + struct device *dev = core->dev_fw ? core->dev_fw : core->dev; > Maybe: > > struct device *fw_dev = core->dev_fw ?: core->dev; > > and preserve *dev to be the main Iris device? That's better, ack. Thanks, Vishnu Reddy. > Konrad