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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTMwMDAzOSBTYWx0ZWRfXx2aohMt+nD6y qCSESbQ288N/LTXjntPHZW+nUNfSk/pKaS/X+K3yBqWYz5eO6Vt9/uyHx670AAl5ArJd9VTSSaJ O/zt+pQOPmP+oqbUJ8AeZ54yfHtvaf0= X-Proofpoint-GUID: XE3v5V-mRL-_LNUyRpwaKl6kdCpeZH_1 X-Authority-Analysis: v=2.4 cv=W9GtxhWk c=1 sm=1 tr=0 ts=6abcdca2 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=OKysoguTPNU6ormpymcA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTMwMDAzOSBTYWx0ZWRfX6Gw1YYode5py 1v3ZxHj3I+IqzSPy44jogV4gvTalrVWcflyg3aBS+iKZy0zf6/1lybg65Tzwh0fi594LZrRzydy O1NN4Yg199jnWiHSRpHB20RwuQFcvN3F7XTlv3B0NguE05nEs15ebqlCZ7ZVAi0Zfp3CDmDwGUJ G934Xk1oOK/oNru94BoDs1GpFERsTSLC8hn2ZA58/OtaBPooiy6r6TBQOqTMzawH4wsIFAuMI+8 ctniuGSB2OGaTKcSiVF4+glTAIoijXia5oXOIVQRQ/OZXvDTTk4Bay8LYRJ4VLZnt1exr3W+Rc3 xYBk6D1FOAJA5VmvX/0CgZwes7kejnHY9gxjyglgu7qjh7mRWvMn2dMSxpKx1rFJXrK0zAjYzyh O8ksLiReAXIwuAbzeLm8RtqVLgzMFHS6t2tNR71vm73nlX58yVf3CrS8NXfQdlr2SXwg1iuYTLH BZLc1Q9fiXRc+qBzSUg== X-Proofpoint-ORIG-GUID: XE3v5V-mRL-_LNUyRpwaKl6kdCpeZH_1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-30_01,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609300039 On 9/28/26 7:29 AM, Sivansh Gupta wrote: > Mailbox hardware registers are 64 bit wide, but the interrupt handler > currently reads only 32 bits with readl() at offset 0x4 (upper 32 > bits). This returns an incorrect value, while reading using readq() > returns the expected value. > > Use readq() to access the 64 bit register and pass the expected value > to the mailbox client. > > Fixes: 0e2a9a03106c ("mailbox: Add support for QTI CPUCP mailbox controller") > Signed-off-by: Sivansh Gupta > --- > v3: > - Removed references to an out of tree driver to focus on the incorrect > value returned by readl() > https://lore.kernel.org/all/93ce8588-7500-45da-9b9a-424c202590cf@oss.qualcomm.com/#t > > v2: > - Expanded the commit message to explain why this change is required. > > drivers/mailbox/qcom-cpucp-mbox.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp-mbox.c > index 862e45e8fbd5..0b584d9aad6c 100644 > --- a/drivers/mailbox/qcom-cpucp-mbox.c > +++ b/drivers/mailbox/qcom-cpucp-mbox.c > @@ -61,7 +61,7 @@ static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data) > status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); > > for_each_set_bit(i, (unsigned long *)&status, cpucp->mbox.num_chans) { > - u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); This still retains the writel() later on > + u64 val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i)); This will alter the indices of the mailbox channels, but it's ""fine"" because it's always zero for the existing platforms.. Konrad