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From: Jianjun Wang <jianjun.wang@mediatek.com>
To: Rob Herring <robh@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	<linux-pci@vger.kernel.org>, <linux-mediatek@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	"Ryder Lee" <ryder.lee@mediatek.com>, <Rex-BC.Chen@mediatek.com>,
	<TingHan.Shen@mediatek.com>, <Liju-clr.Chen@mediatek.com>,
	<Jian.Yang@mediatek.com>
Subject: Re: [PATCH v2] dt-bindings: PCI: mediatek-gen3: Add support for MT8188 and MT8195
Date: Mon, 1 Aug 2022 09:39:22 +0800	[thread overview]
Message-ID: <989faa34506ab4db8b8ce6eae5457ad07b1a2dee.camel@mediatek.com> (raw)
In-Reply-To: <20220729225320.GA82746-robh@kernel.org>

Hi Rob,

Thanks for your comment.

On Fri, 2022-07-29 at 16:53 -0600, Rob Herring wrote:
> On Fri, Jul 29, 2022 at 11:33:31AM +0800, Jianjun Wang wrote:
> > MT8188 and MT8195 are ARM platform SoCs with the same PCIe IP as
> > MT8192.
> > 
> > Also add new clock name "peri_mem" since the MT8188 and MT8195 use
> > clock
> > "peri_mem" instead of "top_133m".
> > 
> > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> > ---
> > Changes in v2:
> > Merge two patches into one.
> > ---
> >  .../bindings/pci/mediatek-pcie-gen3.yaml      | 51
> > +++++++++++++++----
> >  1 file changed, 40 insertions(+), 11 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-
> > gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-
> > gen3.yaml
> > index 0499b94627ae..038e25ae0be7 100644
> > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > @@ -43,12 +43,16 @@ description: |+
> >    each set has its own address for MSI message, and supports 32
> > MSI vectors
> >    to generate interrupt.
> >  
> > -allOf:
> > -  - $ref: /schemas/pci/pci-bus.yaml#
> > -
> >  properties:
> >    compatible:
> > -    const: mediatek,mt8192-pcie
> > +    oneOf:
> > +      - items:
> > +          - enum:
> > +              - mediatek,mt8188-pcie
> > +              - mediatek,mt8195-pcie
> > +          - const: mediatek,mt8192-pcie
> > +      - items:
> > +          - const: mediatek,mt8192-pcie
> >  
> >    reg:
> >      maxItems: 1
> > @@ -78,13 +82,7 @@ properties:
> >      maxItems: 6
> >  
> >    clock-names:
> > -    items:
> > -      - const: pl_250m
> > -      - const: tl_26m
> > -      - const: tl_96m
> > -      - const: tl_32k
> > -      - const: peri_26m
> > -      - const: top_133m
> > +    maxItems: 6
> >  
> >    assigned-clocks:
> >      maxItems: 1
> > @@ -126,9 +124,40 @@ required:
> >    - interrupts
> >    - ranges
> >    - clocks
> > +  - clock-names
> >    - '#interrupt-cells'
> >    - interrupt-controller
> >  
> > +allOf:
> > +  - $ref: /schemas/pci/pci-bus.yaml#
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - mediatek,mt8188-pcie
> > +              - mediatek,mt8195-pcie
> > +    then:
> > +      properties:
> > +        clock-names:
> > +          items:
> > +            - const: pl_250m
> > +            - const: tl_26m
> > +            - const: tl_96m
> > +            - const: tl_32k
> > +            - const: peri_26m
> > +            - const: peri_mem
> > +    else:
> > +      properties:
> > +        clock-names:
> > +          items:
> > +            - const: pl_250m
> > +            - const: tl_26m
> > +            - const: tl_96m
> > +            - const: tl_32k
> > +            - const: peri_26m
> > +            - const: top_133m
> 
> I'm not sure it's worth enforcing just the last clock name. Just do:
> 
> enum: [ peri_mem, top_133m ]
> 
> And key in the top level.
OK, I'll use "enum" to add the new clock name in the next version.

Thanks.
> 
> Rob


      reply	other threads:[~2022-08-01  1:40 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-29  3:33 Jianjun Wang
2022-07-29 22:53 ` Rob Herring
2022-08-01  1:39   ` Jianjun Wang [this message]

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