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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ace6e4cd79dsm920573466b.38.2025.04.30.06.09.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 30 Apr 2025 06:09:43 -0700 (PDT) Message-ID: <98a4ad20-c141-4280-801e-015dafd1fb39@oss.qualcomm.com> Date: Wed, 30 Apr 2025 15:09:41 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFT v6 2/5] drm/msm/adreno: Add speedbin data for SM8550 / A740 To: neil.armstrong@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Dmitry Baryshkov , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio References: <20250430-topic-smem_speedbin_respin-v6-0-954ff66061cf@oss.qualcomm.com> <20250430-topic-smem_speedbin_respin-v6-2-954ff66061cf@oss.qualcomm.com> <13cd20c6-f758-45ff-82d1-4fd663d1698c@linaro.org> <886d979d-c513-4ab8-829e-4a885953079a@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 62g4wT1HOSwIcpojaDFA5u3MknO-ErE5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDMwMDA5NCBTYWx0ZWRfX3zhAFuI5UfH7 aXsx6Ie41vW6QJl/Kog/wZ2X5/GjRNnXwiCTcZmWS6hLN13UIosdp8fAKctxtAYJVN9mvjpxG0F Z4K4xeqridnt+Ez07TkjJUAklbeUycPOaNvB+SCTtUQrZ6NnP/UDBej/a9u8Wl8bkIF/usQgQK6 PgBkLvYWHPFziBJtxwnUN2XU8W/j7rYixZ9X+p4daPr13IJcf5scG0Ik4GeLHDb5cD1mz7nA37X hIsxr+h88eTFwcNR4yxERkKmrXZmungzFRORpXk0ffN1sRuYaB7uyw7mKOQyc2M2EufL05e404L 6cQt1lMoS9tec6MAi4jx3uYaTYsig4I3RrjUeVMn47JvtcfVtTQIAheEcesJAHXXNtQQq+rv2CB i5uzVTT7OlfirbLzUP2OX3EVqEuafS+YgvxZYyUQmVQoPuhu17jFpsAwtCMWEikjbEmxWSa7 X-Authority-Analysis: v=2.4 cv=b5qy4sGx c=1 sm=1 tr=0 ts=68122119 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=KKAkSRfTAAAA:8 a=aak9J4RPMLM6hOP-xocA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 62g4wT1HOSwIcpojaDFA5u3MknO-ErE5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-30_04,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 mlxscore=0 impostorscore=0 malwarescore=0 spamscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504300094 On 4/30/25 2:49 PM, neil.armstrong@linaro.org wrote: > On 30/04/2025 14:35, Konrad Dybcio wrote: >> On 4/30/25 2:26 PM, neil.armstrong@linaro.org wrote: >>> Hi, >>> >>> On 30/04/2025 13:34, Konrad Dybcio wrote: >>>> From: Konrad Dybcio >>>> >>>> Add speebin data for A740, as found on SM8550 and derivative SoCs. >>>> >>>> For non-development SoCs it seems that "everything except FC_AC, FC_AF >>>> should be speedbin 1", but what the values are for said "everything" are >>>> not known, so that's an exercise left to the user.. >>>> >>>> Reviewed-by: Dmitry Baryshkov >>>> Signed-off-by: Konrad Dybcio >>>> --- >>>>    drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 8 ++++++++ >>>>    1 file changed, 8 insertions(+) >>>> >>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> index 53e2ff4406d8f0afe474aaafbf0e459ef8f4577d..61daa331567925e529deae5e25d6fb63a8ba8375 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> @@ -11,6 +11,9 @@ >>>>    #include "a6xx.xml.h" >>>>    #include "a6xx_gmu.xml.h" >>>>    +#include >>>> +#include >>>> + >>>>    static const struct adreno_reglist a612_hwcg[] = { >>>>        {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222}, >>>>        {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, >>>> @@ -1431,6 +1434,11 @@ static const struct adreno_info a7xx_gpus[] = { >>>>            }, >>>>            .address_space_size = SZ_16G, >>>>            .preempt_record_size = 4192 * SZ_1K, >>>> +        .speedbins = ADRENO_SPEEDBINS( >>>> +            { ADRENO_SKU_ID(SOCINFO_FC_AC), 0 }, >>>> +            { ADRENO_SKU_ID(SOCINFO_FC_AF), 0 }, >>>> +            /* Other feature codes (on prod SoCs) should match to speedbin 1 */ >>> >>> I'm trying to understand this sentence. because reading patch 4, when there's no match >>> devm_pm_opp_set_supported_hw() is simply never called so how can it match speedbin 1 ? >> >> What I'm saying is that all other entries that happen to be possibly >> added down the line are expected to be speedbin 1 (i.e. BIT(1)) >> >>> Before this change the fallback was speedbin = BIT(0), but this disappeared. >> >> No, the default was to allow speedbin mask ~(0U) > > Hmm no: > >     supp_hw = fuse_to_supp_hw(info, speedbin); > >     if (supp_hw == UINT_MAX) { >         DRM_DEV_ERROR(dev, >             "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", >             speedbin); >         supp_hw = BIT(0); /* Default */ >     } > >     ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); >     if (ret) >         return ret; Right, that's my own code even.. in any case, the kernel can't know about the speed bins that aren't defined and here we only define bin0, which doesn't break things the kernel isn't aware about hw with bin1 with or without this change so it effectively doesn't matter Konrad