Re: [PATCH v2 03/15] dt-bindings: display: mediatek: add EXDMA yaml for MT8196

["CK Hu (胡俊光)" <ck.hu@mediatek.com>]

On Fri, 2025-03-21 at 17:33 +0800, paul-pl.chen wrote:
> From: Paul-pl Chen <paul-pl.chen@mediatek.com>
> 
> Add mediatek,exdma.yaml to support EXDMA for MT8196.
> The MediaTek display overlap extended DMA engine, namely
> OVL_EXDMA or EXDMA, primarily functions as a DMA engine
> for reading data from DRAM with various DRAM footprints
> and data formats.
> 
> Signed-off-by: Paul-pl Chen <paul-pl.chen@mediatek.com>
> ---
>  .../bindings/dma/mediatek,exdma.yaml          | 70 +++++++++++++++++++
>  1 file changed, 70 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/mediatek,exdma.yaml
> 
> diff --git a/Documentation/devicetree/bindings/dma/mediatek,exdma.yaml b/Documentation/devicetree/bindings/dma/mediatek,exdma.yaml
> new file mode 100644
> index 000000000000..de7f8283bb48
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/mediatek,exdma.yaml
> @@ -0,0 +1,70 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/dma/mediatek,exdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!jH_-2I8NkTUX90vbZGjduUAo4on8DsCGFTrVX5jUdxL_zpKt5PSPRGm31otPZ4wIDzI2h9HFGbF4DC5jPw1nejo$ 
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!jH_-2I8NkTUX90vbZGjduUAo4on8DsCGFTrVX5jUdxL_zpKt5PSPRGm31otPZ4wIDzI2h9HFGbF4DC5jr1jxJoQ$ 
> +
> +title: MediaTek display overlap extended DMA engine
> +
> +maintainers:
> +  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
> +  - Philipp Zabel <p.zabel@pengutronix.de>
> +
> +description:
> +  The MediaTek display overlap extended DMA engine, namely OVL_EXDMA or EXDMA,
> +  primarily functions as a DMA engine for reading data from DRAM with various
> +  DRAM footprints and data formats. For input sources in certain color formats
> +  and color domains, OVL_EXDMA also includes a color transfer function
> +  to process pixels into a consistent color domain.
> +
> +properties:
> +  compatible:
> +    const: mediatek,mt8196-exdma
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  mediatek,larb:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description: |
> +      A phandle to the local arbiters node in the current SoCs.
> +      Refer to bindings/memory-controllers/mediatek,smi-larb.yaml.
> +
> +  iommus:
> +    maxItems: 1
> +
> +  '#dma-cells':
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - power-domains
> +  - mediatek,larb
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        disp_ovl0_exdma2: dma-controller@32850000 {
> +            compatible = "mediatek,mt8196-exdma";
> +            reg = <0 0x32850000 0 0x1000>;
> +            clocks = <&ovlsys_config_clk 13>;
> +            power-domains = <&hfrpsys 12>;
> +            mediatek,larb = <&smi_larb0>;

larb is controlled by iommu, and exdma has already point to iommu.
OVL also not point to larb, so it's not necessary to point to larb here.

Regards,
CK

> +            iommus = <&mm_smmu 144>;
> +            #dma-cells = <1>;
> +        };
> +    };