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Bottomley" , "open list:UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER..." , open list References: <20250116091150.1167739-1-quic_ziqichen@quicinc.com> <20250116091150.1167739-3-quic_ziqichen@quicinc.com> <20250119072204.6arlcagxzdgawb4n@thinkpad> Content-Language: en-US From: Ziqi Chen In-Reply-To: <20250119072204.6arlcagxzdgawb4n@thinkpad> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: wwRfGgS8tJAcjUjp52c6siYcCgmOt8NY X-Proofpoint-GUID: wwRfGgS8tJAcjUjp52c6siYcCgmOt8NY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-20_02,2025-01-20_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 spamscore=0 mlxscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501200100 Hi Mani, Thanks for you review~ On 1/19/2025 3:22 PM, Manivannan Sadhasivam wrote: > On Thu, Jan 16, 2025 at 05:11:43PM +0800, Ziqi Chen wrote: >> From: Can Guo >> >> If OPP V2 is used, devfreq clock scaling may scale clock amongst more than >> two freqs. > > Same comment as previous patch. > please see my response in previous patch. >> In the case of scaling up, the devfreq may decide to scale the >> clock to an intermidiate freq base on load, but the clock scale up pre >> change operation uses settings for the max clock freq unconditionally. Fix >> it by passing the target_freq to clock scale up pre change so that the >> correct settings for the target_freq can be used. >> >> In the case of scaling down, the clock scale down post change operation >> is doing fine, because it reads the actual clock rate to tell freq, but to >> keep symmetry with clock scale up pre change operation, just use the >> target_freq instead of reading clock rate. >> >> Co-developed-by: Ziqi Chen >> Signed-off-by: Ziqi Chen >> Signed-off-by: Can Guo >> --- >> drivers/ufs/host/ufs-qcom.c | 23 ++++++++++++----------- >> 1 file changed, 12 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c >> index b6eef975dc46..1e8a23eb8c13 100644 >> --- a/drivers/ufs/host/ufs-qcom.c >> +++ b/drivers/ufs/host/ufs-qcom.c >> @@ -97,7 +97,7 @@ static const struct __ufs_qcom_bw_table { >> }; >> >> static void ufs_qcom_get_default_testbus_cfg(struct ufs_qcom_host *host); >> -static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up); >> +static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq); >> >> static struct ufs_qcom_host *rcdev_to_ufs_host(struct reset_controller_dev *rcd) >> { >> @@ -524,7 +524,7 @@ static int ufs_qcom_link_startup_notify(struct ufs_hba *hba, >> return -EINVAL; >> } >> >> - err = ufs_qcom_set_core_clk_ctrl(hba, true); >> + err = ufs_qcom_set_core_clk_ctrl(hba, ULONG_MAX); >> if (err) >> dev_err(hba->dev, "cfg core clk ctrl failed\n"); >> /* >> @@ -1231,7 +1231,7 @@ static int ufs_qcom_set_clk_40ns_cycles(struct ufs_hba *hba, >> return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_VS_CORE_CLK_40NS_CYCLES), reg); >> } >> >> -static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up) >> +static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, unsigned long freq) >> { >> struct ufs_qcom_host *host = ufshcd_get_variant(hba); >> struct list_head *head = &hba->clk_list_head; >> @@ -1245,10 +1245,11 @@ static int ufs_qcom_set_core_clk_ctrl(struct ufs_hba *hba, bool is_scale_up) >> !strcmp(clki->name, "core_clk_unipro")) { >> if (!clki->max_freq) >> cycles_in_1us = 150; /* default for backwards compatibility */ >> - else if (is_scale_up) >> + else if (freq == ULONG_MAX) >> cycles_in_1us = ceil(clki->max_freq, (1000 * 1000)); >> else >> - cycles_in_1us = ceil(clk_get_rate(clki->clk), (1000 * 1000)); >> + cycles_in_1us = ceil(freq, (1000 * 1000)); > > Consider switching to HZ_PER_MHZ in a separate patch later Sure, Thanks for suggestion, will update in next version. > > - Mani -Ziqi >