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Wed, 10 Dec 2025 13:11:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IHbBXzDiOXtSdMaF2b7fdEH4r75SwGnJGdOCk5npK2CmpZqJ2QEVbCBDzn/HBSCMic4HCMWZw== X-Received: by 2002:a05:6a00:b91:b0:77f:efd:829b with SMTP id d2e1a72fcca58-7f22e0a30bfmr3813195b3a.22.1765401060352; Wed, 10 Dec 2025 13:11:00 -0800 (PST) Received: from [192.168.1.5] ([106.222.234.96]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7f4c4aa91d0sm402642b3a.32.2025.12.10.13.10.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Dec 2025 13:11:00 -0800 (PST) Message-ID: <9971bd9b-88db-4628-b36b-de50c1619396@oss.qualcomm.com> Date: Thu, 11 Dec 2025 02:40:52 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/6] arm64: dts: qcom: sm6150: Add gpu and rgmu nodes To: Dmitry Baryshkov Cc: Konrad Dybcio , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Jessica Zhang , Dan Carpenter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jie Zhang References: <20251122-qcs615-spin-2-v3-0-9f4d4c87f51d@oss.qualcomm.com> <20251122-qcs615-spin-2-v3-5-9f4d4c87f51d@oss.qualcomm.com> <8560ad26-4756-4c2a-97c3-2c5c0695172c@oss.qualcomm.com> <6fa1da5d-9ea7-4d72-a03a-82edc4bef099@oss.qualcomm.com> <3gqq3w6ovy5srgvabyeugsjbwrhaxmjvicykhjmlcxd74gtsaf@5u6wvvzeq52z> <90bc84e7-19ca-450d-b41f-fd96367e8cce@oss.qualcomm.com> <2e5sqv2gnxdfwnfsepzdkchxip5zdeamp6bzbamq6kbk77kr3p@u5i4rrnrywno> Content-Language: en-US From: Akhil P Oommen In-Reply-To: <2e5sqv2gnxdfwnfsepzdkchxip5zdeamp6bzbamq6kbk77kr3p@u5i4rrnrywno> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 5w2dxU4h_D4EtibIbU7qMdrC3DRtnqc- X-Authority-Analysis: v=2.4 cv=Y6P1cxeN c=1 sm=1 tr=0 ts=6939e1e5 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=CcjbiXvC7xLhAd+qVKJczA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=iOf4mfiAVVuFJQUywdwA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 5w2dxU4h_D4EtibIbU7qMdrC3DRtnqc- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEwMDE3NCBTYWx0ZWRfXxoFgNRz6uBNx P/JpX31VLkrmO7r90OIdobHaaUAVsaE/9Narh2D27EJYqmsjbnWqDrlGVig892SD9/SdIpwSh9Y GK3ukuLobGWXlH/LmpxO4N6dXtbF6qNqcG5JqtXhnc0hI6vrGLnc+H8QnMv2eJSTrPfc+zmfCon /P2n4+bkJ5HXpYJqce7CUGLs8HQuMGEtXSORT9MK8TgQ6YCSrq3E+KqRqJUOvBf9W5xpflRov5y w9mTEfIvdDgDfhhiAgMGDPcmtgO0s6sPd9pUm+z15xLGZpV1KzO6GWLAFsZ3FYSRxKny4oXAiY8 2Z5ZxtltbxeUw4zN6CH0RsTYorlFd6GP/nNDNw4YdzsDVcEkvXL3PZMNDvMXITR57mau/7XGHPb ZDeoOs75wV6v+M6AIM0eox01bTGCuA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-10_03,2025-12-09_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 adultscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 phishscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512100174 On 12/6/2025 2:04 AM, Dmitry Baryshkov wrote: > On Fri, Dec 05, 2025 at 03:59:09PM +0530, Akhil P Oommen wrote: >> On 12/4/2025 7:49 PM, Dmitry Baryshkov wrote: >>> On Thu, Dec 04, 2025 at 03:43:33PM +0530, Akhil P Oommen wrote: >>>> On 11/26/2025 6:12 AM, Dmitry Baryshkov wrote: >>>>> On Sat, Nov 22, 2025 at 03:03:10PM +0100, Konrad Dybcio wrote: >>>>>> On 11/21/25 10:52 PM, Akhil P Oommen wrote: >>>>>>> From: Jie Zhang >>>>>>> >>>>>>> Add gpu and rgmu nodes for qcs615 chipset. >>>>>>> >>>>>>> Signed-off-by: Jie Zhang >>>>>>> Signed-off-by: Akhil P Oommen >>>>>>> --- >>>>>> >>>>>> [...] >>>>>> >>>>>>> + gpu_opp_table: opp-table { >>>>>>> + compatible = "operating-points-v2"; >>>>>>> + >>>>>>> + opp-845000000 { >>>>>>> + opp-hz = /bits/ 64 <845000000>; >>>>>>> + required-opps = <&rpmhpd_opp_turbo>; >>>>>>> + opp-peak-kBps = <7050000>; >>>>>>> + }; >>>>>> >>>>>> I see another speed of 895 @ turbo_l1, perhaps that's for speedbins >>>>>> or mobile parts specifically? >>>>> >>>>> msm-4.14 defines 7 speedbins for SM6150. Akhil, I don't see any of them >>>>> here. >>>> >>>> The IoT/Auto variants have a different frequency plan compared to the >>>> mobile variant. I reviewed the downstream code and this aligns with that >>>> except the 290Mhz corner. We can remove that one. >>>> >>>> Here we are describing the IoT variant of Talos. So we can ignore the >>>> speedbins from the mobile variant until that is supported. >>> >>> No, we are describing just Talos, which hopefully covers both mobile and >>> non-mobile platforms. >> >> We cannot assume that. >> >> Even if we assume that there is no variation in silicon, the firmware >> (AOP, TZ, HYP etc) is different between mobile and IoT version. So it is >> wise to use the configuration that is commercialized, especially when it >> is power related. > > How does it affect the speed bins? I'd really prefer if we: > - describe OPP tables and speed bins here > - remove speed bins cell for the Auto / IoT boards > - make sure that the driver uses the IoT bin if there is no speed bin > declared in the GPU. > The frequency plan is different between mobile and IoT. Are you proposing to describe a union of OPP table from both mobile and IoT? Another wrinkle we need to address is that, so far, we have never had a dt binding where opp-supp-hw property exist without the speedbin cells. And that adds a bit of complexity on the driver side because, today, the KMD relies on the presence of speed bin cells to decide whether to select bin via opp_supp_hw API or not. Also, we may have to reserve this combination (opp bins without speedbin cells) to help KMD detect that it should use socinfo APIs instead of speedbin cells on certain chipsets. -Akhil