Re: [PATCH] arm64: dts: qcom: add missing cache node for cpu1

[Neil Armstrong <neil.armstrong@linaro.org>]

On 09/01/2025 19:30, Konrad Dybcio wrote:
> On 9.01.2025 4:24 PM, Neil Armstrong wrote:
>> Add the missing l2-cache node for the cpu1
>>
>> Fixes: 20eb2057b3e4 ("arm64: dts: qcom: sm8650: change labels to lower-case")
>> Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi")
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
> 
> subject: missing `sm8650:`

Damn

> 
>>   arch/arm64/boot/dts/qcom/sm8650.dtsi | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> index 86684cb9a9325618ddb74458621cf4bbdc1cc0d1..832f3a2c400e8348847bc24b27397e2a0dc08db8 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> @@ -119,6 +119,13 @@ cpu1: cpu@100 {
>>   			qcom,freq-domain = <&cpufreq_hw 0>;
>>   
>>   			#cooling-cells = <2>;
>> +
>> +			l2_100: l2-cache {
>> +				compatible = "cache";
>> +				cache-level = <2>;
>> +				cache-unified;
>> +				next-level-cache = <&l3_0>;
>> +			};
>>   		};
> 
> You likely wanted to hook up this new node to CPU1 as well.
> 
> Reading some Arm docs [1], it seems like with A520 specifically, both shared
> and unique cache slices are permitted, depending on whether they're
> implemented as single- or dual-core complexes (not to be confused with
> multi-threading)
> 
> [2] suggests CA720s always have their own cache pools
> 
> In 8650's case, the slowest cluster has a shared L2 cache, whereas cores 2-7
> have their own pools, so this patch is incorrect.

Damn you're right, so the cpu1 cache should be linked to the cpu0 cache somehow

Thanks,
Neil

> 
> Konrad
> 
> [1] https://developer.arm.com/documentation/102517/0004/The-Cortex-A520--core/Cortex-A520--core-configuration-options
> [2] https://developer.arm.com/documentation/102530/0001/L2-memory-system