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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae35363b1fdsm131221366b.14.2025.06.27.06.58.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Jun 2025 06:58:02 -0700 (PDT) Message-ID: <99b9e6aa-36b4-456c-ba46-6e1207cc1019@oss.qualcomm.com> Date: Fri, 27 Jun 2025 15:57:59 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V3 1/4] dt-bindings: mmc: Add dll-hsr-list for HS400 and HS200 modes To: Krzysztof Kozlowski , Ram Prakash Gupta , Sachin Gupta , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adrian Hunter , Bhupesh Sharma Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_cang@quicinc.com, quic_nguyenb@quicinc.com, quic_bhaskarv@quicinc.com, quic_mapa@quicinc.com, quic_narepall@quicinc.com, quic_nitirawa@quicinc.com, quic_sartgarg@quicinc.com References: <20250122094707.24859-1-quic_sachgupt@quicinc.com> <20250122094707.24859-2-quic_sachgupt@quicinc.com> <72b02fd1-5195-4bb0-b01d-5481b49a5680@kernel.org> <379e9199-4a9e-cd38-20cb-0fbd76fa33b3@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=eLYTjGp1 c=1 sm=1 tr=0 ts=685ea36d cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=COk6AnOGAAAA:8 a=v25VQKkRDONtiw5Uw7IA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: e-jidb_FQkNkim-BPCTn7you47Vyl6ad X-Proofpoint-ORIG-GUID: e-jidb_FQkNkim-BPCTn7you47Vyl6ad X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjI3MDExNSBTYWx0ZWRfXy+72IwVR0cDu 2IFJF8OcSz7hxOXeV4/Kp1J2IO6xQPYdWJQkGPvtLee0FySwKjxA1HsESPcfPHPvUM2x3iQfXrS Q0Bc6z1IuLPDgAHeEo6qSojyHovSsgUtAs9D0622Zg+1aFzcdqJsSyQxmzJEt3y+YRKeJo4AWPy SKJXhi2su7J6TwVkee90yjjbYXC92cjDB59qoO5hWq8gLdgQhh86UDJujPrRPrtkWWPnRcruRco uJcxSIbjR9paoknj0b5SZv6JVTgpXIaUeHkK8Q8qKEv+28MpLy98lYa3x+wM1nBUR3ritVsi/4O hFo8yTalCVDCsMVpFnz/7Bakzr89JNEJxymHUDCcg1ONcebON3m5haN57WoHkoiYCAsLQKea/Ek +KklN9y6qJb10Fw9gY/G2sMwU/djWHiqL3afWHsMRW3JdOrwUfL+M1O7eqTS28hujszvTwuA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-27_04,2025-06-26_05,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 mlxscore=0 clxscore=1015 mlxlogscore=999 suspectscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506270115 On 6/26/25 7:42 PM, Krzysztof Kozlowski wrote: > On 26/06/2025 16:16, Ram Prakash Gupta wrote: >> On 1/22/2025 3:56 PM, Krzysztof Kozlowski wrote: >>> On 22/01/2025 10:47, Sachin Gupta wrote: >>>> Document the 'dll-hsr-list' property for MMC device tree bindings. >>>> The 'dll-hsr-list' property defines the DLL configurations for HS400 >>>> and HS200 modes. >>>> >>>> Signed-off-by: Sachin Gupta >>>> --- >>>> Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 5 +++++ >>>> 1 file changed, 5 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml >>>> index 8b393e26e025..65dc3053df75 100644 >>>> --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml >>>> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml >>>> @@ -133,6 +133,11 @@ properties: >>>> $ref: /schemas/types.yaml#/definitions/uint32 >>>> description: platform specific settings for DLL_CONFIG reg. >>>> >>>> + qcom,dll-hsr-list: >>>> + maxItems: 10 >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> uint32 has only one item. Anyway, there is already DLL there, so don't >>> duplicate or explain why this is different. Explain also why this is not >>> deducible from the compatible. >> > > > Timeline still amazes me. I will be grumpy on this thread. > >> I will change it to reflect array from uint32. >> There is change with artanis DLL hw addition where it need total of 5 entries >> (dll_config, dll_config_2, dll_config_3, dll_usr_ctl, ddr_config) >> for each HS400 and HS200 modes, hence the new addition in dt. And these values >> are not fixed and varies for every SoC, hence this needs to be passed through >> dt like it was passed earlier for qcom,dll-config & qcom,ddr-config. > > > Eh, no. That's not a valid reason. It's still SoC deducible. Don't bring > your downstream practices here, but remove EVERYTHING from downstream > and start doing things like upstream is doing. QC SoCs have between 0 and 4 SDHCI instances, each one potentially requiring different tuning, let's keep this data in DT Konrad