From: Jon Kohler <jon@nutanix.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: "seanjc@google.com" <seanjc@google.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"mingo@redhat.com" <mingo@redhat.com>,
"bp@alien8.de" <bp@alien8.de>,
"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
"x86@kernel.org" <x86@kernel.org>,
"hpa@zytor.com" <hpa@zytor.com>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Jonathan Corbet <corbet@lwn.net>,
"open list:DOCUMENTATION" <linux-doc@vger.kernel.org>,
"ken@codelabs.ch" <ken@codelabs.ch>,
"Alexander.Grest@microsoft.com" <Alexander.Grest@microsoft.com>,
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"xiaoyao.li@intel.com" <xiaoyao.li@intel.com>,
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Subject: Re: [PATCH 5/8] KVM: x86/mmu: bootstrap support for Intel MBEC
Date: Tue, 3 Mar 2026 19:04:52 +0000 [thread overview]
Message-ID: <9A277ADB-E2DD-4CA3-AB8E-DF019F73EA06@nutanix.com> (raw)
In-Reply-To: <4a4bd216-3cdf-4098-8a59-a4cbceb31677@redhat.com>
> On Mar 3, 2026, at 12:54 PM, Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> On 12/23/25 06:47, Jon Kohler wrote:
>> Extend kvm_mmu_page_role access bitfield from 3 to 4, where the 4th bit
>> will be used to track user executable pages with Intel mode-based
>> execute control (MBEC).
>> Extend SPTE generation and introduce shadow_ux value to account for
>> user and kernel executable distinctions under MBEC.
>
> While MBEC has a different definition of the bits, GMET is essentially SMEP (except that AMD couldn't retrofit it into hCR4.SMEP due to how NPT handles the U bit). I wonder if it's possible to handle MBEC as SMEP as well, with some additional handling of the SPTEs (with shadox_x_mask and shadow_ux_mask taking the functionality of shadow_nx_mask and shadow_u_mask) but no large changes to the MMU.
>
> This should be a much simpler patch set if it can be made to work. I'll take a look.
>
> Paolo
Thanks, Paolo. Certainly if we can make this simpler, I’m all for it.
I appreciate any help we can get on this one.
Happy to test out additional approaches, as we’ve got the Windows
performance regression test for this completely automated on our side
to study the impact one way or the other.
Thanks again,
Jon
next prev parent reply other threads:[~2026-03-03 19:06 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-23 5:47 [PATCH 0/8] KVM: VMX: Introduce Intel Mode-Based Execute Control (MBEC) Jon Kohler
2025-12-23 5:47 ` [PATCH 1/8] KVM: TDX/VMX: rework EPT_VIOLATION_EXEC_FOR_RING3_LIN into PROT_MASK Jon Kohler
2025-12-23 5:47 ` [PATCH 2/8] KVM: x86/mmu: remove SPTE_PERM_MASK Jon Kohler
2025-12-23 5:47 ` [PATCH 3/8] KVM: x86/mmu: adjust MMIO generation bit allocation and allowed mask Jon Kohler
2025-12-23 5:47 ` [PATCH 4/8] KVM: x86/mmu: update access permissions from ACC_ALL to ACC_RWX Jon Kohler
2025-12-23 5:47 ` [PATCH 5/8] KVM: x86/mmu: bootstrap support for Intel MBEC Jon Kohler
2026-03-03 17:54 ` Paolo Bonzini
2026-03-03 19:04 ` Jon Kohler [this message]
2025-12-23 5:47 ` [PATCH 6/8] KVM: VMX: enhance EPT violation handler for MBEC Jon Kohler
2025-12-23 5:48 ` [PATCH 7/8] KVM: VMX: allow MBEC with EVMCS Jon Kohler
2025-12-23 5:48 ` [PATCH 8/8] KVM: nVMX: advertise MBEC and setup mmu has_mbec Jon Kohler
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