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Mon, 19 Oct 2026 06:12:38 -0700 (PDT) X-Received: by 2002:a05:6102:26d2:b0:7c3:83a9:edc9 with SMTP id ada2fe7eead31-7cc367447afmr1369837137.1.1792415558381; Mon, 19 Oct 2026 06:12:38 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c4090dcf100sm353774066b.15.2026.10.19.06.12.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Oct 2026 06:12:37 -0700 (PDT) Message-ID: <9a058856-2dbb-4ea6-93f0-ed4d2ccd3ba7@oss.qualcomm.com> Date: Mon, 19 Oct 2026 15:12:34 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] drm/msm/a6xx: Program the PDC sequencer on Adreno 620 To: patches@brar.si, Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20261016-adreno-a620-v1-0-4a7ed6210d7d@brar.si> <20261016-adreno-a620-v1-3-4a7ed6210d7d@brar.si> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261016-adreno-a620-v1-3-4a7ed6210d7d@brar.si> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: BkPhs_rcBv0sKV1FITt_YT9RkeaOJzjQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE5MDA1MiBTYWx0ZWRfXxx1kTpERxRuE pHyXPdcWtniEryxy9G2YlohX3NTGjtz5ezQxiW/vn0eoySzwk7BlQSu4oa4gTMfyEN3prL83P2T lcOxkc+I2KR1zbddhNClF7okOpfYpRubQjdtWYD4gRkcab2u4J2tqldtlJ8lYKsOh4HxvIGQJri Wh1DkgzShqdY8iNop+Zyvy2X920Od3aN0BWoYQ6z+ZyG/HdyIdsjFtbgj3FxBTZVB3PZoNG7zPg aBZsSMoPuXaLpoVXiW5IP3p3mloOaW1OgWiDozTZ7Xl6N2lO1xZHbWQ/6Lnornn6gDp4HikQc8K oByLLeSEDqJkDLUpDeUm8yoNBG2PcSDkf/onRxmaf3RoKPNG7ok+oeJrpwD7rHS+lL/Bmc7a5Yi +bQBBmsYCfLvtXGAlmdKP9dd8wlk6m7DiKSHI980lSBqRAYzTL4OjxpjXQvnFq2Eg5smRGEm+H/ c0bQZnIsy0YwfY+HeMw== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE5MDA1MiBTYWx0ZWRfX3paqn1jW/+Sq SaJZvDljLoFyh/7ahX2zcqSAa2rHscKP3JVHxfUGYunR8aNmBjw8K5jaVk1wQp9tQZtBNh3u7Y9 kuZ9++y2jmua5Zi8J2YfNWeir/3UC44= X-Proofpoint-GUID: BkPhs_rcBv0sKV1FITt_YT9RkeaOJzjQ X-Authority-Analysis: v=2.4 cv=OaANnRTY c=1 sm=1 tr=0 ts=6ad61748 cx=c_pps a=JIY1xp/sjQ9K5JH4t62bdg==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=ODsmY_3wxSbvKopP8XUA:9 a=QEXdDO2ut3YA:10 a=tNoRWFLymzeba-QzToBc:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-19_03,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 bulkscore=0 adultscore=0 clxscore=1015 malwarescore=0 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610190052 On 10/16/26 2:53 PM, Ishu Brar via B4 Relay wrote: > From: Ishu Brar > > Unlike the rest of the A650 family, the A620 does not get its PDC set up > by AOP (the downstream devicetree has no pdc_in_aop for it). Without the > sequence, the RSC never acks the second power-up ("Unable to power on > the GPU RSC") and the device hangs. > > Program the sequence from the driver, taking the xo, mx and cx resource > addresses from cmd-db instead of the hardcoded ones. > > Assisted-by: Claude > Signed-off-by: Ishu Brar > --- There's also this hunk in kgsl: _regwrite(cfg, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2, xo_resource_addr); _regwrite(cfg, PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x0); ==== if (vrm_resource_addr && adreno_is_a620(adreno_dev)) { _regwrite(cfg, PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET * 3, 0x10108); _regwrite(cfg, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 3, vrm_resource_addr + 0x4); _regwrite(cfg, PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET * 3, 0x0); } ==== _regwrite(cfg, PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); _regwrite(cfg, PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); _regwrite(cfg, PDC_GPU_TCS3_CONTROL, 0); _regwrite(cfg, PDC_GPU_TCS3_CMD0_MSGID, 0x10108); if vrm.soc exists (presumably because a620 shipped on a number of socs?) Konrad