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Fri, 6 Feb 2026 12:46:25 -0600 Received: from [128.247.81.105] (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 616IkP6X1360117; Fri, 6 Feb 2026 12:46:25 -0600 Message-ID: <9a127d54-c028-4b20-9b08-42da5c235c53@ti.com> Date: Fri, 6 Feb 2026 12:46:25 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] soc: ti: k3-socinfo: Add support for AM62P variants via NVMEM To: Andrew Davis , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Santosh Shilimkar CC: , , References: <20260204213746.2589028-1-jm@ti.com> <20260204213746.2589028-3-jm@ti.com> <25ced9af-b103-4cd3-9b31-42b188fcad60@ti.com> <528b107d-e2ff-4970-9484-24a6acca8308@ti.com> Content-Language: en-US From: Judith Mendez In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231D:EE_|DS7PR10MB4925:EE_ X-MS-Office365-Filtering-Correlation-Id: 2a18f71e-36d1-4fca-6745-08de65b008b5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: oA6YAHPv1bQ2CDJDLN95MxSYk+U+YVqNFDT7AyBYJ9B8WQVaEdfxOqfmLitBTdDEl9vpppFsZOVjvg8+uToZricUfnyYHcbApsmbchNG2bGbAA0v2cevxGNR4vFjrIQ6fdNr2dQ4fA1BSyQQPfOrvQ6BdZhslKdu8ojxcHD6mlIZFeRC3PWXOq8MBcrHI3wghqEjCn+HinkG5KJ5Am0cUelm5PtwgKRy/xf4eZltcz/ryZJ45zCoiMsEmABsxBMQuV4l+l/C+2yAJCB3uGkIBuL+GFL6quoqOgGPexbKJRulP/RFnXHwOwepqffiH4x3DAOixfwsPCKvIWF/5COaEcxYE4fyCSG1u7P0y7UHXlLIHlwOyMNyccqxDIIKyInDfExbEGIuZLQVEPUbQXnaIGTlzugso2hPoESSkla85q2KYtFS0jh54qNyCpOgVPPL X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Feb 2026 18:46:26.6622 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2a18f71e-36d1-4fca-6745-08de65b008b5 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.195];Helo=[flwvzet201.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR10MB4925 On 2/6/26 10:50 AM, Andrew Davis wrote: > On 2/5/26 6:38 PM, Judith Mendez wrote: >> Andrew, >> >> On 2/4/26 3:54 PM, Andrew Davis wrote: >>> On 2/4/26 3:37 PM, Judith Mendez wrote: >>>> Add support for detecting AM62P silicon revisions. >>>> >>>> On AM62P, silicon revision is discovered with GP_SW1 register instead >>>> of JTAGID register. Use the NVMEM framework to read GP_SW1 from the >>>> gpsw-efuse nvmem provider to determine SoC revision. >>>> >>>> Signed-off-by: Judith Mendez >>>> --- >>>>   drivers/soc/ti/k3-socinfo.c | 48 +++++++++++++++++++++++++++++++++ >>>> +--- >>>>   1 file changed, 45 insertions(+), 3 deletions(-) >>>> >>>> diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c >>>> index 42275cb5ba1c8..4b6947a9ceb4d 100644 >>>> --- a/drivers/soc/ti/k3-socinfo.c >>>> +++ b/drivers/soc/ti/k3-socinfo.c >>>> @@ -6,6 +6,7 @@ >>>>    */ >>>>   #include >>>> +#include >>>>   #include >>>>   #include >>>>   #include >>>> @@ -25,6 +26,9 @@ >>>>   #define CTRLMMR_WKUP_JTAGID_VARIANT_SHIFT    (28) >>>>   #define CTRLMMR_WKUP_JTAGID_VARIANT_MASK    GENMASK(31, 28) >>>> +#define GP_SW1_VALID_BIT            BIT(4) >>>> +#define GP_SW1_ADR_MASK            GENMASK(3, 0) >>>> + >>>>   #define CTRLMMR_WKUP_JTAGID_PARTNO_SHIFT    (12) >>>>   #define CTRLMMR_WKUP_JTAGID_PARTNO_MASK        GENMASK(27, 12) >>>> @@ -70,6 +74,29 @@ static const char * const am62lx_rev_string_map[] >>>> = { >>>>       "1.0", "1.1", >>>>   }; >>>> +static const char * const am62p_gpsw_rev_string_map[] = { >>>> +    "1.0", "1.1", "1.2", >>>> +}; >>>> + >>>> +static int >>>> +k3_chipinfo_get_gpsw_variant(struct platform_device *pdev) >>>> +{ >>>> +    struct device *dev = &pdev->dev; >>>> +    u32 gpsw_val, adr_val = 0; >>>> +    int ret; >>>> + >>>> +    ret = nvmem_cell_read_u32(dev, "gpsw1", &gpsw_val); >>>> +    if (ret) >>>> +        return ret; >>>> + >>>> +    if (!(gpsw_val & GP_SW1_VALID_BIT)) >>>> +        return 0; >>> >>> Return -1 here so you will get the warning message about setting >>> default SR1.0. >> >> Actually, thinking about this some more... If valid bit is zero, that >> means that we have detected SR1.0. > > To me a valid bit set to zero means the register is not valid.. If you are > saying that bit actually signals SR1.0 then that bit is not well named. > > Although if the whole register is simply all zeros for SR1.0 then do you > actually need this check at all? When you do extract the revision from > the lowest bits (gpsw_val & GP_SW1_ADR_MASK) the result will also be 0, > which is the SR1.0 value anyway. Ok, sounds like a plan. Will drop valid bit parsing and respin the series, thanks. ~ Judith