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> } > > +static int geni_i2c_resources_init(struct geni_i2c_dev *gi2c) > +{ > + int ret; > + > + ret = geni_se_resources_init(&gi2c->se); > + if (ret) > + return ret; > + > + ret = geni_i2c_clk_map_idx(gi2c); > + if (ret) > + return dev_err_probe(gi2c->se.dev, ret, "Invalid clk frequency %d Hz\n", > + gi2c->clk_freq_out); > + > + return geni_icc_set_bw_ab(&gi2c->se, GENI_DEFAULT_BW, GENI_DEFAULT_BW, > + Bps_to_icc(gi2c->clk_freq_out)); > +} > + > static int geni_i2c_probe(struct platform_device *pdev) > { > struct geni_i2c_dev *gi2c; > @@ -1061,16 +1078,6 @@ static int geni_i2c_probe(struct platform_device *pdev) > > desc = device_get_match_data(&pdev->dev); > > - if (desc && desc->has_core_clk) { > - gi2c->core_clk = devm_clk_get(dev, "core"); > - if (IS_ERR(gi2c->core_clk)) > - return PTR_ERR(gi2c->core_clk); > - } > - > - gi2c->se.clk = devm_clk_get(dev, "se"); > - if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev)) > - return PTR_ERR(gi2c->se.clk); > - > ret = device_property_read_u32(dev, "clock-frequency", > &gi2c->clk_freq_out); > if (ret) { > @@ -1085,16 +1092,15 @@ static int geni_i2c_probe(struct platform_device *pdev) > if (gi2c->irq < 0) > return gi2c->irq; > > - ret = geni_i2c_clk_map_idx(gi2c); > - if (ret) > - return dev_err_probe(dev, ret, "Invalid clk frequency %d Hz\n", > - gi2c->clk_freq_out); > - > gi2c->adap.algo = &geni_i2c_algo; > init_completion(&gi2c->done); > spin_lock_init(&gi2c->lock); > platform_set_drvdata(pdev, gi2c); > > + ret = geni_i2c_resources_init(gi2c); > + if (ret) > + return ret; > + > /* Keep interrupts disabled initially to allow for low-power modes */ > ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN, > dev_name(dev), gi2c); > @@ -1107,23 +1113,6 @@ static int geni_i2c_probe(struct platform_device *pdev) > gi2c->adap.dev.of_node = dev->of_node; > strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); > > - ret = geni_icc_get(&gi2c->se, desc ? desc->icc_ddr : "qup-memory"); > - if (ret) > - return ret; > - /* > - * Set the bus quota for core and cpu to a reasonable value for > - * register access. > - * Set quota for DDR based on bus speed. > - */ > - gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; > - gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; > - if (!desc || desc->icc_ddr) > - gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out); > - > - ret = geni_icc_set_bw(&gi2c->se); > - if (ret) > - return ret; > - > gi2c->suspended = 1; > pm_runtime_set_suspended(gi2c->se.dev); > pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);