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Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH 06/14] spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width for dwc-ssi Content-Language: en-US To: Conor.Dooley@microchip.com, fancer.lancer@gmail.com, mail@conchuod.ie Cc: airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, thierry.reding@gmail.com, sam@ravnborg.org, Eugeniy.Paltsev@synopsys.com, vkoul@kernel.org, lgirdwood@gmail.com, broonie@kernel.org, daniel.lezcano@linaro.org, palmer@dabbelt.com, palmer@rivosinc.com, tglx@linutronix.de, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, masahiroy@kernel.org, geert@linux-m68k.org, niklas.cassel@wdc.com, dillon.minfei@gmail.com, jee.heng.sia@intel.com, joabreu@synopsys.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, alsa-devel@alsa-project.org, linux-spi@vger.kernel.org, linux-riscv@lists.infradead.org References: <20220618123035.563070-1-mail@conchuod.ie> <20220618123035.563070-7-mail@conchuod.ie> <20220620205654.g7fyipwytbww5757@mobilestation> <61b0fb86-078d-0262-b142-df2984ce0f97@microchip.com> From: Damien Le Moal Organization: Western Digital Research In-Reply-To: <61b0fb86-078d-0262-b142-df2984ce0f97@microchip.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 6/21/22 06:06, Conor.Dooley@microchip.com wrote: > On 20/06/2022 21:56, Serge Semin wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >> >> On Sat, Jun 18, 2022 at 01:30:28PM +0100, Conor Dooley wrote: >>> From: Conor Dooley >>> >>> snps,dwc-ssi-1.01a has a single user - the Canaan k210, which uses a >>> width of 4 for spi-{r,t}x-bus-width. Update the binding to reflect >>> this. >>> >>> Signed-off-by: Conor Dooley >>> --- >>> .../bindings/spi/snps,dw-apb-ssi.yaml | 48 ++++++++++++++----- >>> 1 file changed, 35 insertions(+), 13 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml >>> index e25d44c218f2..f2b9e3f062cd 100644 >>> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml >>> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml >>> @@ -135,19 +135,41 @@ properties: >>> of the designware controller, and the upper limit is also subject to >>> controller configuration. >>> >>> -patternProperties: >>> - "^.*@[0-9a-f]+$": >>> - type: object >>> - properties: >>> - reg: >>> - minimum: 0 >>> - maximum: 3 >>> - >>> - spi-rx-bus-width: >>> - const: 1 >>> - >>> - spi-tx-bus-width: >>> - const: 1 >>> +if: >>> + properties: >>> + compatible: >>> + contains: >>> + const: snps,dwc-ssi-1.01a >>> + >>> +then: >>> + patternProperties: >>> + "^.*@[0-9a-f]+$": >>> + type: object >>> + properties: >>> + reg: >>> + minimum: 0 >>> + maximum: 3 >>> + >>> + spi-rx-bus-width: >>> + const: 4 >>> + >>> + spi-tx-bus-width: >>> + const: 4 >>> + >>> +else: >>> + patternProperties: >>> + "^.*@[0-9a-f]+$": >>> + type: object >>> + properties: >>> + reg: >>> + minimum: 0 >>> + maximum: 3 >>> + >>> + spi-rx-bus-width: >>> + const: 1 >>> + >>> + spi-tx-bus-width: >>> + const: 1 >> >> You can just use a more relaxed constraint "enum: [1 2 4 8]" here > > 8 too? sure. > >> irrespective from the compatible string. The modern DW APB SSI >> controllers of v.4.* and newer also support the enhanced SPI Modes too >> (Dual, Quad and Octal). Since the IP-core version is auto-detected at >> run-time there is no way to create a DT-schema correctly constraining >> the Rx/Tx SPI bus widths. So let's keep the >> compatible-string-independent "patternProperties" here but just extend >> the set of acceptable "spi-rx-bus-width" and "spi-tx-bus-width" >> properties values. > > SGTM! > >> >> Note the DW APB SSI/AHB SSI driver currently doesn't support the >> enhanced SPI modes. So I am not sure whether the multi-lines Rx/Tx SPI >> bus indeed works for Canaan K210 AHB SSI controller. AFAICS from the >> DW APB SSI v4.01a manual the Enhanced SPI mode needs to be properly >> activated by means of the corresponding CSR. So most likely the DW AHB >> SSI controllers need some specific setups too. > > hmm, well I'll leave that up to people that have Canaan hardware! I will test this series. > Thanks, > Conor. > >> >> -Sergey >> >>> >>> unevaluatedProperties: false >>> >>> -- >>> 2.36.1 >>> > -- Damien Le Moal Western Digital Research