From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86149C2D0C4 for ; Tue, 10 Dec 2019 03:57:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6268820726 for ; Tue, 10 Dec 2019 03:57:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727119AbfLJD5L (ORCPT ); Mon, 9 Dec 2019 22:57:11 -0500 Received: from mail-sz.amlogic.com ([211.162.65.117]:38470 "EHLO mail-sz.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726619AbfLJD5J (ORCPT ); Mon, 9 Dec 2019 22:57:09 -0500 Received: from [10.28.19.135] (10.28.19.135) by mail-sz.amlogic.com (10.28.11.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1591.10; Tue, 10 Dec 2019 11:57:40 +0800 Subject: Re: [PATCH] arm64: dts: a1: add saradc controller To: Kevin Hilman , Neil Armstrong , Martin Blumenstingl CC: Rob Herring , Jonathan Cameron , Jerome Brunet , Qianggui Song , Jianxin Pan , Jian Hu , , , , , References: <1575358332-44866-1-git-send-email-xingyu.chen@amlogic.com> <7hpngxqfa7.fsf@baylibre.com> From: Xingyu Chen Message-ID: <9a2ddfa3-28f3-7d15-bb25-5b84078b77c7@amlogic.com> Date: Tue, 10 Dec 2019 11:57:39 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <7hpngxqfa7.fsf@baylibre.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-GB X-Originating-IP: [10.28.19.135] X-ClientProxiedBy: mail-sz.amlogic.com (10.28.11.5) To mail-sz.amlogic.com (10.28.11.5) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Kevin On 2019/12/10 6:56, Kevin Hilman wrote: > Xingyu Chen writes: > >> The saradc controller in Meson-A1 is the same as the Meson-G12 series SoCs, >> so we use the same compatible string. >> >> Signed-off-by: Xingyu Chen >> >> --- >> This patch is based on A1 clock patchset at [0]. >> >> [0] https://lore.kernel.org/linux-amlogic/20191129144605.182774-1-jian.hu@amlogic.com >> --- >> arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 15 +++++++++++++++ >> 1 file changed, 15 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> index 7210ad0..cad1756 100644 >> --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi >> @@ -93,6 +93,21 @@ >> clock-names = "xtal", "pclk", "baud"; >> status = "disabled"; >> }; >> + >> + saradc: adc@2c00 { >> + compatible = "amlogic,meson-g12a-saradc", >> + "amlogic,meson-saradc"; >> + reg = <0x0 0x2c00 0x0 0x48>; > Why 0x48 here? AXG uses 0x38 and you're not adding any more registers > to this driver. Thanks for you review. The saradc introduces 4 new registers (as shown below) begin with g12a platform, and these registers are used to save the sampling value of corresponding channel. In other words, we can choose fifo or new registers to save sampling value, but it is not supported by the current driver. dout register  |---> fifo                          |---> channel regs -|                                                            |--- channel-0                                                            |--- channel-1                                                            | ...                                                            | --- channel-7 AO_SAR_ADC_CHNL01：saving sampling data of channel 0/1 AO_SAR_ADC_CHNL23:   saving sampling data of channel 2/3 AO_SAR_ADC_CHNL45:   saving sampling data of channel 4/5 AO_SAR_ADC_CHNL67:   saving sampling data of channel 6/7 This patch use the 0x48 to describe the registers length just follow the file meson-g12-common.dtsi. and it doesn't affect the driver because of the mapped regiter length is limited by max_register member in struct regmap_config. I can replace 0x48 with 0x38 in next patch if necessary. > Kevin > > . >