From: Paolo Bonzini <pbonzini@redhat.com>
To: "Xu, Like" <like.xu@intel.com>,
Stephane Eranian <eranian@google.com>,
Peter Zijlstra <peterz@infradead.org>
Cc: Like Xu <like.xu@linux.intel.com>,
kvm@vger.kernel.org,
Sean Christopherson <sean.j.christopherson@intel.com>,
Vitaly Kuznetsov <vkuznets@redhat.com>,
Wanpeng Li <wanpengli@tencent.com>,
Jim Mattson <jmattson@google.com>, Joerg Roedel <joro@8bytes.org>,
Kan Liang <kan.liang@linux.intel.com>,
luwei.kang@intel.com, Thomas Gleixner <tglx@linutronix.de>,
"Wang, Wei W" <wei.w.wang@intel.com>,
Tony Luck <tony.luck@intel.com>,
Mark Gross <mgross@linux.intel.com>,
Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] perf/intel: Remove Perfmon-v4 counter_freezing support
Date: Tue, 26 Jan 2021 10:51:39 +0100 [thread overview]
Message-ID: <9a85e154-d552-3478-6e99-3f693b3da7ed@redhat.com> (raw)
In-Reply-To: <2ce24056-0711-26b3-a62c-3bedc88d7aa7@intel.com>
On 11/11/20 03:42, Xu, Like wrote:
> Hi Peter,
>
> On 2020/11/11 4:52, Stephane Eranian wrote:
>> On Tue, Nov 10, 2020 at 7:37 AM Peter Zijlstra<peterz@infradead.org>
>> wrote:
>>> On Tue, Nov 10, 2020 at 04:12:57PM +0100, Peter Zijlstra wrote:
>>>> On Mon, Nov 09, 2020 at 10:12:37AM +0800, Like Xu wrote:
>>>>> The Precise Event Based Sampling(PEBS) supported on Intel Ice Lake
>>>>> server
>>>>> platforms can provide an architectural state of the instruction
>>>>> executed
>>>>> after the instruction that caused the event. This patch set enables
>>>>> the
>>>>> the PEBS via DS feature for KVM (also non) Linux guest on the Ice
>>>>> Lake.
>>>>> The Linux guest can use PEBS feature like native:
>>>>>
>>>>> # perf record -e instructions:ppp ./br_instr a
>>>>> # perf record -c 100000 -e instructions:pp ./br_instr a
>>>>>
>>>>> If the counter_freezing is not enabled on the host, the guest PEBS
>>>>> will
>>>>> be disabled on purpose when host is using PEBS facility. By default,
>>>>> KVM disables the co-existence of guest PEBS and host PEBS.
> Thanks Stephane for clarifying the use cases for Freeze-on-[PMI|Overflow].
>
> Please let me express it more clearly.
>
> The goal of the whole patch set is to enable guest PEBS, regardless of
> whether the counter_freezing is frozen or not. By default, it will not
> support both the guest and the host to use PEBS at the same time.
>
> Please continue reviewing the patch set, especially for the slow path
> we proposed this time and related host perf changes:
>
> - add intel_pmu_handle_guest_pebs() to __intel_pmu_pebs_event();
> - add switch MSRs (PEBS_ENABLE, DS_AREA, DATA_CFG) to
> intel_guest_get_msrs();
> - the construction of incoming parameters for
> perf_event_create_kernel_counter();
>
> I believe if you understand the general idea, the comments will be very
> valuable.
What is the state of this work? I was expecting a new version that
doesn't use counter_freezing. However, I see that counter_freezing is
still in there, so this patch from Peter has never been applied.
Paolo
next prev parent reply other threads:[~2021-01-26 11:57 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-09 2:12 [PATCH RFC v2 00/17] KVM: x86/pmu: Add support to enable Guest PEBS via DS Like Xu
2020-11-09 2:12 ` [PATCH v2 01/17] KVM: x86/pmu: Set MSR_IA32_MISC_ENABLE_EMON bit when vPMU is enabled Like Xu
2020-11-09 2:12 ` [PATCH v2 02/17] KVM: vmx/pmu: Use IA32_PERF_CAPABILITIES to adjust features visibility Like Xu
2020-11-09 2:12 ` [PATCH v2 03/17] KVM: x86/pmu: Introduce the ctrl_mask value for fixed counter Like Xu
2020-11-09 2:12 ` [PATCH v2 04/17] perf: x86/ds: Handle guest PEBS overflow PMI and inject it to guest Like Xu
2020-11-17 14:35 ` Peter Zijlstra
2020-11-18 16:15 ` Like Xu
2020-11-18 18:07 ` Peter Zijlstra
2020-11-19 1:36 ` Xu, Like
2020-11-27 2:14 ` Xu, Like
2020-11-30 10:49 ` Peter Zijlstra
2020-12-01 1:25 ` Xu, Like
2020-11-09 2:12 ` [PATCH v2 05/17] KVM: x86/pmu: Reprogram guest PEBS event to emulate guest PEBS counter Like Xu
2020-11-17 14:41 ` Peter Zijlstra
2020-11-18 16:18 ` Like Xu
2020-11-09 2:12 ` [PATCH v2 06/17] KVM: x86/pmu: Add IA32_PEBS_ENABLE MSR emulation for extended PEBS Like Xu
2020-11-09 2:12 ` [PATCH v2 07/17] KVM: x86/pmu: Add IA32_DS_AREA MSR emulation to manage guest DS buffer Like Xu
2020-11-09 2:12 ` [PATCH v2 08/17] KVM: x86/pmu: Add PEBS_DATA_CFG MSR emulation to support adaptive PEBS Like Xu
2020-11-09 2:12 ` [PATCH v2 09/17] KVM: x86: Set PEBS_UNAVAIL in IA32_MISC_ENABLE when PEBS is enabled Like Xu
2020-11-09 2:12 ` [PATCH v2 10/17] KVM: x86/pmu: Expose CPUIDs feature bits PDCM, DS, DTES64 Like Xu
2020-11-09 2:12 ` [PATCH v2 11/17] KVM: x86/pmu: Adjust precise_ip to emulate Ice Lake guest PDIR counter Like Xu
2020-11-09 2:12 ` [PATCH v2 12/17] KVM: x86/pmu: Disable guest PEBS when counters are cross-mapped Like Xu
2020-11-09 2:12 ` [PATCH RFC v2 13/17] KVM: x86/pmu: Add hook to emulate pebs for cross-mapped counters Like Xu
2020-11-09 2:12 ` [PATCH RFC v2 14/17] KVM: vmx/pmu: Limit pebs_interrupt_threshold in the guest DS area Like Xu
2020-11-09 2:12 ` [PATCH RFC v2 15/17] KVM: vmx/pmu: Rewrite applicable_counters field in the guest PEBS record Like Xu
2020-11-09 2:12 ` [PATCH RFC v2 16/17] KVM: x86/pmu: Save guest pebs reset value when a pebs counter is configured Like Xu
2020-11-09 2:12 ` [PATCH RFC v2 17/17] KVM: x86/pmu: Adjust guest DS pebs reset counter values for mapped counter Like Xu
2020-11-10 15:12 ` [PATCH RFC v2 00/17] KVM: x86/pmu: Add support to enable Guest PEBS via DS Peter Zijlstra
2020-11-10 15:37 ` [PATCH] perf/intel: Remove Perfmon-v4 counter_freezing support Peter Zijlstra
2020-11-10 20:52 ` Stephane Eranian
2020-11-11 2:42 ` Xu, Like
2021-01-26 9:51 ` Paolo Bonzini [this message]
2021-01-26 10:36 ` Peter Zijlstra
2021-01-26 11:35 ` Xu, Like
2021-01-26 11:59 ` Paolo Bonzini
2020-11-11 8:38 ` Peter Zijlstra
2020-11-16 3:22 ` Like Xu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=9a85e154-d552-3478-6e99-3f693b3da7ed@redhat.com \
--to=pbonzini@redhat.com \
--cc=eranian@google.com \
--cc=jmattson@google.com \
--cc=joro@8bytes.org \
--cc=kan.liang@linux.intel.com \
--cc=kvm@vger.kernel.org \
--cc=like.xu@intel.com \
--cc=like.xu@linux.intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=luwei.kang@intel.com \
--cc=mgross@linux.intel.com \
--cc=peterz@infradead.org \
--cc=sean.j.christopherson@intel.com \
--cc=srinivas.pandruvada@linux.intel.com \
--cc=tglx@linutronix.de \
--cc=tony.luck@intel.com \
--cc=vkuznets@redhat.com \
--cc=wanpengli@tencent.com \
--cc=wei.w.wang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®