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Mon, 20 Jan 2025 12:12:49 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50KCCm5e006797 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 20 Jan 2025 12:12:48 GMT Received: from [10.239.155.136] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 20 Jan 2025 04:12:43 -0800 Message-ID: <9aab1765-224e-4f84-9366-a1b46e5260b7@quicinc.com> Date: Mon, 20 Jan 2025 20:12:39 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 8/8] ARM: dts: msm: Use Operation Points V2 for UFS on SM8650 To: Krzysztof Kozlowski , , , , , , , , , , CC: , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "open list:ARM/QUALCOMM SUPPORT" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list References: <20250116091150.1167739-1-quic_ziqichen@quicinc.com> <20250116091150.1167739-9-quic_ziqichen@quicinc.com> <5b419c6a-ba22-41d3-bd5e-869d422f3c5d@kernel.org> Content-Language: en-US From: Ziqi Chen In-Reply-To: <5b419c6a-ba22-41d3-bd5e-869d422f3c5d@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: eLu7vWzDkpWVCfPRGrIgu4LQey7OUqIK X-Proofpoint-GUID: eLu7vWzDkpWVCfPRGrIgu4LQey7OUqIK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-20_02,2025-01-20_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 suspectscore=0 bulkscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 priorityscore=1501 clxscore=1011 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501200102 Hi Krzysztof, Thanks for review and comments~ As Neil has submitted a similar patch: https://lore.kernel.org/all/20250115-topic-sm8x50-upstream-dt-icc-update-v1-10-eaa8b10e2af7@linaro.org/ I will withdraw this patch in next version. -Ziqi On 1/16/2025 5:22 PM, Krzysztof Kozlowski wrote: > On 16/01/2025 10:11, Ziqi Chen wrote: >> Use Operation Points V2 for UFS on SM8650 so that multi-level >> clock/gear scaling can be possible. >> >> Co-developed-by: Can Guo >> Signed-off-by: Can Guo >> Signed-off-by: Ziqi Chen > > Please don't send downstream code directly, but fix it first. Actually - > rework it 100%. > > Please use subject prefixes matching the subsystem. You can get them for > example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory > your patch is touching. For bindings, the preferred subjects are > explained here: > https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters > >> --- >> arch/arm64/boot/dts/qcom/sm8650.dtsi | 51 +++++++++++++++++++++++----- >> 1 file changed, 43 insertions(+), 8 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> index 01ac3769ffa6..5466f1217f64 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> @@ -2557,18 +2557,11 @@ ufs_mem_hc: ufs@1d84000 { >> "tx_lane0_sync_clk", >> "rx_lane0_sync_clk", >> "rx_lane1_sync_clk"; >> - freq-table-hz = <100000000 403000000>, >> - <0 0>, >> - <0 0>, >> - <100000000 403000000>, >> - <100000000 403000000>, >> - <0 0>, >> - <0 0>, >> - <0 0>; >> >> resets = <&gcc GCC_UFS_PHY_BCR>; >> reset-names = "rst"; >> >> + operating-points-v2 = <&ufs_opp_table>; >> interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS >> &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> @@ -2590,6 +2583,48 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> #reset-cells = <1>; >> >> status = "disabled"; >> + >> + ufs_opp_table: opp-table { >> + compatible = "operating-points-v2"; > > > Messed indentation. > >> + // LOW_SVS > > > Drop > >> + opp-100000000 { >> + opp-hz = /bits/ 64 <100000000>, >> + /bits/ 64 <0>, > > Messed alignment. > >> + /bits/ 64 <0>, >> + /bits/ 64 <100000000>, >> + /bits/ 64 <0>, >> + /bits/ 64 <0>, >> + /bits/ 64 <0>, > > > > > Best regards, > Krzysztof