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x-category=clean score=-100 state=0; x-google-dkim=fail (body has been altered; 2048-bit rsa key) header.d=1e100.net header.i=@1e100.net header.b=L4sGzOj6; x-ptr=pass x-ptr-helo=vger.kernel.org x-ptr-lookup=vger.kernel.org; x-return-mx=pass smtp.domain=vger.kernel.org smtp.result=pass smtp_org.domain=kernel.org smtp_org.result=pass smtp_is_org_domain=no header.domain=gmail.com header.result=pass header_is_org_domain=yes Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932481AbeCMXV3 (ORCPT ); Tue, 13 Mar 2018 19:21:29 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:35369 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753017AbeCMXVY (ORCPT ); Tue, 13 Mar 2018 19:21:24 -0400 X-Google-Smtp-Source: AG47ELuOLbQLQ3rbKzH0KuyG4c4/MNuNtJGbUgcfmcMj8Fucpdk0SvUfRwTeF/Y8ogfkUf2Zzafqcg== Subject: Re: [PATCH v2 2/3] phy: phy-mtk-tphy: add configurable parameters for slew rate calibrate To: Chunfeng Yun , Kishon Vijay Abraham I Cc: Rob Herring , Mark Rutland , Ian Campbell , Ryder Lee , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org References: <123d1a24659be168d0b040de4a67612acacf66f1.1520832210.git.chunfeng.yun@mediatek.com> From: Matthias Brugger Message-ID: <9abfde61-f81e-1a17-7ff9-85a7017f649b@gmail.com> Date: Wed, 14 Mar 2018 00:21:20 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <123d1a24659be168d0b040de4a67612acacf66f1.1520832210.git.chunfeng.yun@mediatek.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-usb-owner@vger.kernel.org X-Mailing-List: linux-usb@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On 03/12/2018 06:25 AM, Chunfeng Yun wrote: > There are two parameters, ref_clk and coefficient, for U2 slew rate > calibrate which may vary on different SoCs, here allow them to be > configurable > > Signed-off-by: Chunfeng Yun Reviewed-by: Matthias Brugger > --- > drivers/phy/mediatek/phy-mtk-tphy.c | 20 +++++++++++++++----- > 1 file changed, 15 insertions(+), 5 deletions(-) > > diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c > index 6073c25..38c281b 100644 > --- a/drivers/phy/mediatek/phy-mtk-tphy.c > +++ b/drivers/phy/mediatek/phy-mtk-tphy.c > @@ -306,6 +306,8 @@ struct mtk_tphy { > const struct mtk_phy_pdata *pdata; > struct mtk_phy_instance **phys; > int nphys; > + int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ > + int src_coef; /* coefficient for slew rate calibrate */ > }; > > static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, > @@ -360,16 +362,17 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, > writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); > > if (fm_out) { > - /* ( 1024 / FM_OUT ) x reference clock frequency x 0.028 */ > - tmp = U3P_FM_DET_CYCLE_CNT * U3P_REF_CLK * U3P_SLEW_RATE_COEF; > - tmp /= fm_out; > + /* ( 1024 / FM_OUT ) x reference clock frequency x coef */ > + tmp = tphy->src_ref_clk * tphy->src_coef; > + tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out; > calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR); > } else { > /* if FM detection fail, set default value */ > calibration_val = 4; > } > - dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d\n", > - instance->index, fm_out, calibration_val); > + dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n", > + instance->index, fm_out, calibration_val, > + tphy->src_ref_clk, tphy->src_coef); > > /* set HS slew rate */ > tmp = readl(com + U3P_USBPHYACR5); > @@ -1041,6 +1044,13 @@ static int mtk_tphy_probe(struct platform_device *pdev) > tphy->u3phya_ref = NULL; > } > > + tphy->src_ref_clk = U3P_REF_CLK; > + tphy->src_coef = U3P_SLEW_RATE_COEF; > + /* update parameters of slew rate calibrate if exist */ > + device_property_read_u32(dev, "mediatek,src-ref-clk-mhz", > + &tphy->src_ref_clk); > + device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef); > + > port = 0; > for_each_child_of_node(np, child_np) { > struct mtk_phy_instance *instance; >