From: David Laight <David.Laight@ACULAB.COM>
To: "'Palmer Dabbelt'" <palmer@sifive.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: "patches@groups.riscv.org" <patches@groups.riscv.org>,
Andrew Waterman <andrew@sifive.com>
Subject: RE: [PATCH 3/4] RISC-V: Flush I$ when making a dirty page executable
Date: Tue, 21 Nov 2017 16:57:07 +0000 [thread overview]
Message-ID: <9acaf467a587413a9aa1529ab8cc904e@AcuMS.aculab.com> (raw)
In-Reply-To: <20171120185745.30795-4-palmer@sifive.com>
From: Palmer Dabbelt
> Sent: 20 November 2017 18:58
>
> The RISC-V ISA allows for instruction caches that are not coherent WRT
> stores, even on a single hart. As a result, we need to explicitly flush
> the instruction cache whenever marking a dirty page as executable in
> order to preserve the correct system behavior.
Isn't the I-flush only needed if there has been an unmap since the
previous I-flush?
Since code is rarely unmapped (exec and driver unload come to mind)
the I-flush won't be needed very often.
David
next prev parent reply other threads:[~2017-11-21 16:56 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-20 18:57 RISC-V: User-Visible ABI Cleanup Palmer Dabbelt
2017-11-20 18:57 ` [PATCH 1/4] RISC-V: Remove __vdso_cmpxchg{32,64} symbol versions Palmer Dabbelt
2017-11-20 18:57 ` [PATCH 2/4] RISC-V: Add VDSO entries for clock_get/gettimeofday/getcpu Palmer Dabbelt
2017-11-20 18:57 ` [PATCH 3/4] RISC-V: Flush I$ when making a dirty page executable Palmer Dabbelt
2017-11-21 16:57 ` David Laight [this message]
2017-11-22 17:38 ` [patches] " Palmer Dabbelt
2017-11-22 19:03 ` Andrew Waterman
2017-11-30 20:32 ` [patches] " Olof Johansson
2017-11-30 22:50 ` Palmer Dabbelt
2017-11-20 18:57 ` [PATCH 4/4] RISC-V: Allow userspace to flush the instruction cache Palmer Dabbelt
2017-11-21 15:58 ` RISC-V: User-Visible ABI Cleanup Christoph Hellwig
2017-11-21 16:02 ` Palmer Dabbelt
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