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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH v3] irqchip/gicv3: Workaround for NVIDIA erratum T241-FABRIC-4 Content-Language: en-US To: Marc Zyngier , Catalin Marinas , Will Deacon , Jonathan Corbet , Mark Rutland , Lorenzo Pieralisi , Sudeep Holla , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vikram Sethi , Thierry Reding References: <20230317162636.851085-1-sdonthineni@nvidia.com> From: Shanker Donthineni In-Reply-To: <20230317162636.851085-1-sdonthineni@nvidia.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SJ0PR05CA0015.namprd05.prod.outlook.com (2603:10b6:a03:33b::20) To MN0PR12MB5762.namprd12.prod.outlook.com (2603:10b6:208:375::12) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN0PR12MB5762:EE_|DS0PR12MB7584:EE_ X-MS-Office365-Filtering-Correlation-Id: 8d936004-bb05-42d4-d265-08db2766de22 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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> + unsigned long chip_bmask = 0; > + phys_addr_t phys; > + u32 i; > + > + /* Check JEP106 code for NVIDIA T241 chip (036b:0241) */ > + if ((soc_id < 0) || (soc_id != SMCCC_SOC_ID_T241)) > + return false; > + > + /* Find the chips based on GICR regions PHYS addr */ > + for (i = 0; i < gic_data.nr_redist_regions; i++) { > + chip_bmask |= BIT(FIELD_GET(T241_CHIPN_MASK, > + gic_data.redist_regions[i].phys_base)); > + } Apologies for the oversight on my part, I failed to address the build issue for the 32-bit architecture and mistakenly submitted an incorrect patch. Please ignore this patch and review v4 patch. Correct change: for (i = 0; i < gic_data.nr_redist_regions; i++) { chip_bmask |= BIT(FIELD_GET(T241_CHIPN_MASK, - gic_data.redist_regions[i].phys_base)); + (u64)gic_data.redist_regions[i].phys_base)); -Shaker