From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B14992E0901 for ; Wed, 13 May 2026 20:33:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778704433; cv=none; b=Su66mD6x8WCs99MgCcfVMOfZBASSVMTIl4B8JwJbuOEBUB4tTrLH1vOIbeYqzHaX/0NM0l5fqVmQAv+RbDOd9txljQVCoGpQ9GqelFDzz60b0JY83Vz7ueB2vMy6owlx0ylzuRceaCkUDHS8+D1xzG2td00TYphDKViPODL53ZA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778704433; c=relaxed/simple; bh=XbuGDa7JJ7FVqD5xSNQStR6gz6ySjrTGgL8YslZ2MOY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UZQAKbN8XqLNn1ndZiyTc4LaleobIPyv4bshd2iLlTSeoVh5Rxl6p1wUd61SJqyVlCY2U6mBQUXow0fhFb/dBKafV9mMy0WpmFuJDYs/gKY5qrD6rGx81ocxPJHFBRyF/ngeIm5wHk79FOIb/6lScuxqYHxO34xBo1NF3w700Kw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=oHS+MsNU; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="oHS+MsNU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1778704432; x=1810240432; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XbuGDa7JJ7FVqD5xSNQStR6gz6ySjrTGgL8YslZ2MOY=; b=oHS+MsNUjJ9M+r1YZv72Ts0PFqtf4nvzd/3kp1mA60atqXtFcZAZQuwb zDnoFa2Tsq62xNHX6Sm1HMSrILzMoHZEeY8cWPvwXpOe5Kf75LU5NSfMv T3J5X4I6lnlrQP9/6oF/kDCNQpcitb3Mhd+J+LacRdplDlCZ7Yn9LBiAF pkCJIakapVjp4z/EiMuyaeT7a0Emv1MrWJOBZ5rfyXd1aD658UrJciB3g rzWoUN7NptTDwYFu3QnwC7SeDH2Hr/tlk0Z7zTRObX2pE/JLT6b4eKhDA whLQByHOSdSzDuXNnEKmp8xGeXtEanB/i208bxoBCnkBOgRHKkW1RjuUl Q==; X-CSE-ConnectionGUID: 0OZa9K75SseKqH4UFhsYjA== X-CSE-MsgGUID: XDVtHtarRHmT2f/GVmrVUw== X-IronPort-AV: E=McAfee;i="6800,10657,11785"; a="79623220" X-IronPort-AV: E=Sophos;i="6.23,233,1770624000"; d="scan'208";a="79623220" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2026 13:33:46 -0700 X-CSE-ConnectionGUID: 2uFbUuxzT8qEkaBirVibpg== X-CSE-MsgGUID: 7+U8vwYWS1qQxb+xWNKJpw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,233,1770624000"; d="scan'208";a="238076397" Received: from b04f130c83f2.jf.intel.com ([10.165.154.98]) by orviesa008.jf.intel.com with ESMTP; 13 May 2026 13:33:45 -0700 From: Tim Chen To: Peter Zijlstra , Ingo Molnar , K Prateek Nayak , Vincent Guittot Cc: Chen Yu , Juri Lelli , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Madadi Vineeth Reddy , Hillf Danton , Shrikanth Hegde , Jianyong Wu , Yangyu Chen , Tingyin Duan , Vern Hao , Vern Hao , Len Brown , Tim Chen , Aubrey Li , Zhao Liu , Chen Yu , Adam Li , Aaron Lu , Tim Chen , Josh Don , Gavin Guo , Qais Yousef , Libo Chen , Luo Gengkun , linux-kernel@vger.kernel.org Subject: [Patch v4 12/16] sched/cache: Fix race condition during sched domain rebuild Date: Wed, 13 May 2026 13:39:23 -0700 Message-Id: <9afddf439687f04bb56b46625bd9f153eb8abad5.1778703694.git.tim.c.chen@linux.intel.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Chen Yu sched_cache_active_set_unlocked() checks hardware support without locks: static void sched_cache_active_set(bool locked) { /* hardware does not support */ if (!static_branch_likely(&sched_cache_present)) { _sched_cache_active_set(false, locked); return; } ... If build_sched_domains() runs concurrently during CPU hotplug, it can disable sched_cache_present under sched_domains_mutex and the CPU hotplug lock. If a debugfs write thread evaluates sched_cache_present as true right before that, and then blocks or gets preempted, it might proceed to enable sched_cache_active after the hardware support has been marked as absent. Make it safer by acquiring cpus_read_lock() and sched_domains_mutex_lock() when the user changes sched_cache_active via debugfs. This bug was reported by sashiko. Fixes: 067a31358143 ("sched/cache: Allow the user space to turn on and off cache aware scheduling") Signed-off-by: Chen Yu Co-developed-by: Tim Chen Signed-off-by: Tim Chen --- kernel/sched/debug.c | 4 +++- kernel/sched/sched.h | 2 +- kernel/sched/topology.c | 42 +++++++++++++++-------------------------- 3 files changed, 19 insertions(+), 29 deletions(-) diff --git a/kernel/sched/debug.c b/kernel/sched/debug.c index fe569539e888..ed3a0d65da0c 100644 --- a/kernel/sched/debug.c +++ b/kernel/sched/debug.c @@ -224,7 +224,9 @@ sched_cache_enable_write(struct file *filp, const char __user *ubuf, sysctl_sched_cache_user = val; - sched_cache_active_set_unlocked(); + sched_cache_active_set(); + + *ppos += cnt; return cnt; } diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 27409399137c..45a3b77f46aa 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -4083,7 +4083,7 @@ static inline bool sched_cache_enabled(void) return static_branch_unlikely(&sched_cache_active); } -extern void sched_cache_active_set_unlocked(void); +extern void sched_cache_active_set(void); #endif diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 7248a7279abe..cff5a0ecd64d 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -917,30 +917,19 @@ static bool alloc_sd_llc(const struct cpumask *cpu_map, return false; } -static void _sched_cache_active_set(bool enable, bool locked) -{ - if (enable) { - if (locked) - static_branch_enable_cpuslocked(&sched_cache_active); - else - static_branch_enable(&sched_cache_active); - } else { - if (locked) - static_branch_disable_cpuslocked(&sched_cache_active); - else - static_branch_disable(&sched_cache_active); - } -} - /* * Enable/disable cache aware scheduling according to * user input and the presence of hardware support. + * Expected to be protected by cpus_read_lock() and + * sched_domains_mutex_lock() */ -static void sched_cache_active_set(bool locked) +static void _sched_cache_active_set(void) { /* hardware does not support */ if (!static_branch_likely(&sched_cache_present)) { - _sched_cache_active_set(false, locked); + static_branch_disable_cpuslocked(&sched_cache_active); + if (sched_debug()) + pr_info("%s: cache aware scheduling not supported on this platform\n", __func__); return; } @@ -951,24 +940,23 @@ static void sched_cache_active_set(bool locked) * for now. */ if (sysctl_sched_cache_user) { - _sched_cache_active_set(true, locked); + static_branch_enable_cpuslocked(&sched_cache_active); if (sched_debug()) pr_info("%s: enabling cache aware scheduling\n", __func__); } else { - _sched_cache_active_set(false, locked); + static_branch_disable_cpuslocked(&sched_cache_active); if (sched_debug()) pr_info("%s: disabling cache aware scheduling\n", __func__); } } -static void sched_cache_active_set_locked(void) -{ - return sched_cache_active_set(true); -} - -void sched_cache_active_set_unlocked(void) +void sched_cache_active_set(void) { - return sched_cache_active_set(false); + cpus_read_lock(); + sched_domains_mutex_lock(); + _sched_cache_active_set(); + sched_domains_mutex_unlock(); + cpus_read_unlock(); } /* @@ -3082,7 +3070,7 @@ build_sched_domains(const struct cpumask *cpu_map, struct sched_domain_attr *att else static_branch_disable_cpuslocked(&sched_cache_present); - sched_cache_active_set_locked(); + _sched_cache_active_set(); #endif __free_domain_allocs(&d, alloc_state, cpu_map); -- 2.32.0