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Tue, 15 Feb 2022 01:55:44 -0800 (PST) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id q30sm738704ljc.134.2022.02.15.01.55.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Feb 2022 01:55:44 -0800 (PST) Message-ID: <9b0fbece-8618-6b48-0240-3bab45e54a77@linaro.org> Date: Tue, 15 Feb 2022 12:55:43 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.1 Subject: Re: [PATCH v2] arm64: dts: qcom: sm8450: add interconnect nodes Content-Language: en-GB To: Vinod Koul , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, Andy Gross , Rob Herring , Georgi Djakov , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220203002936.3009402-1-vkoul@kernel.org> From: Dmitry Baryshkov In-Reply-To: <20220203002936.3009402-1-vkoul@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 03/02/2022 03:29, Vinod Koul wrote: > And the various interconnect nodes found in SM8450 SoC and use it for > UFS controller. > > Signed-off-by: Vinod Koul > --- > > Changes in v2: > - Fix the mc_virt node > - Add clk_virt node > - Rebase to rc1 > > arch/arm64/boot/dts/qcom/sm8450.dtsi | 85 ++++++++++++++++++++++++++++ > 1 file changed, 85 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 10c25ad2d0c7..ccc67918c46a 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > #include > > / { > @@ -250,6 +251,18 @@ scm: scm { > }; > }; > > + clk_virt: interconnect@0 { > + compatible = "qcom,sm8450-clk-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + mc_virt: interconnect@1 { > + compatible = "qcom,sm8450-mc-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > memory@a0000000 { > device_type = "memory"; > /* We expect the bootloader to fill in the size */ > @@ -620,6 +633,54 @@ i2c14: i2c@a98000 { > }; > }; > > + config_noc: interconnect@1500000 { > + compatible = "qcom,sm8450-config-noc"; > + reg = <0 0x01500000 0 0x1c000>; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + system_noc: interconnect@1680000 { > + compatible = "qcom,sm8450-system-noc"; > + reg = <0 0x01680000 0 0x1e200>; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + pcie_noc: interconnect@16c0000 { > + compatible = "qcom,sm8450-pcie-anoc"; > + reg = <0 0x016c0000 0 0xe280>; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + aggre1_noc: interconnect@16e0000 { > + compatible = "qcom,sm8450-aggre1-noc"; > + reg = <0 0x016e0000 0 0x1c080>; > + #interconnect-cells = <2>; > + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + aggre2_noc: interconnect@1700000 { > + compatible = "qcom,sm8450-aggre2-noc"; > + reg = <0 0x01700000 0 0x31080>; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, > + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&rpmhcc RPMH_IPA_CLK>; > + }; > + > + mmss_noc: interconnect@1740000 { > + compatible = "qcom,sm8450-mmss-noc"; > + reg = <0 0x01740000 0 0x1f080>; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > tcsr_mutex: hwlock@1f40000 { > compatible = "qcom,tcsr-mutex"; > reg = <0x0 0x01f40000 0x0 0x40000>; > @@ -988,6 +1049,13 @@ cpufreq_hw: cpufreq@17d91000 { > #freq-domain-cells = <1>; > }; > > + gem_noc: interconnect@19100000 { > + compatible = "qcom,sm8450-gem-noc"; > + reg = <0 0x19100000 0 0xbb800>; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > ufs_mem_hc: ufshc@1d84000 { > compatible = "qcom,sm8450-ufshc", "qcom,ufshc", > "jedec,ufs-2.0"; > @@ -1004,6 +1072,9 @@ ufs_mem_hc: ufshc@1d84000 { > > iommus = <&apps_smmu 0xe0 0x0>; > > + interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, As you have #interconnect-cells = <2> for all the NoCs, this should be: interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; > + interconnect-names = "ufs-ddr", "cpu-ufs"; > clock-names = > "core_clk", > "bus_aggr_clk", > @@ -1102,6 +1173,20 @@ usb_1_dwc3: usb@a600000 { > phy-names = "usb2-phy", "usb3-phy"; > }; > }; > + > + nsp_noc: interconnect@320c0000 { > + compatible = "qcom,sm8450-nsp-noc"; > + reg = <0 0x320c0000 0 0x10000>; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + lpass_ag_noc: interconnect@3c40000 { > + compatible = "qcom,sm8450-lpass-ag-noc"; > + reg = <0 0x3c40000 0 0x17200>; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > }; > > timer { -- With best wishes Dmitry